summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* nvc0: handle discontiguous outputs in stream_output_infoChristoph Bumiller2012-01-203-28/+25
|
* mesa: allocate transform_feedback_info::Outputs array dynamicallyChristoph Bumiller2012-01-202-39/+57
| | | | | | | | | | | | The nvc0 gallium driver is advertising 128 MAX_INTERLEAVED_COMPS which made it always assert in the linker when TFB was used since the Outputs array was smaller than that maximum. v2: added assertions NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Paul Berry <[email protected]>
* r600g: fixup AR handling (v5)Dave Airlie2012-01-204-7/+106
| | | | | | | | | | | | | | | | | | | | | | | So it appears R600s (except rv670) do AR handling different using a different opcode. This patch fixes up r600g to work properly on r600. This fixes ~100 piglit tests here (in GLSL1.30 mode) on rv610. v3: add index_mode as per the docs. This still fails any dst relative tests for some reason I can't quite see yet, but it passes a lot more tests than without. v4: add a nop after dst.rel this could be improved using a second pass, where we only insert nops if two instructions are sure to collide. The docs say r600, rv610, rv630 needs this, and not rv670, rs780, rs880, need AMD to confirm rv620, rv635. v5: add is_nop_inst. NOTE: This is a candidate for stable branches. Signed-off-by: Dave Airlie <[email protected]>
* mesa: include arrayobj.h to silence implicit function declaration warningBrian Paul2012-01-201-0/+1
| | | | Caused by commit 7a1e941ebee43cb97a2c77fd2269999b202308a2.
* mesa: Fix and speedup gl_array_object::_MaxElement computation.Mathias Fröhlich2012-01-202-139/+28
| | | | | | | | | | Use a bitmask approach to compute gl_array_object::_MaxElement. To make this work correctly depending on the shader type actually used, make use of the newly introduced typed bitmask getters. With this change I gain about 5% draw time on some osgviewer examples. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Introduce enabled bitfield helper functions.Mathias Froehlich2012-01-202-0/+41
| | | | | | | | | | Depending on the installed shader type, different arrays are used from gl_array_object. Provide helper functions that compute the bitmask of these arrays that are finally enabled for a given shader type. The will be used in a followup change. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Use BITFIELD64_RANGE for VERT_BIT_*_ALL.Mathias Fröhlich2012-01-201-5/+5
| | | | | Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i915g: Fix indentation.Stéphane Marchesin2012-01-191-1/+1
|
* i915g: Fix indentation and comment.Stéphane Marchesin2012-01-191-2/+2
|
* glsl: Fix isinf() for non-C99-compliant compilers.Paul Berry2012-01-191-14/+22
| | | | | | | | | | | | | | | | | | Commit ede60bc4670a8d9c14921c77abee1ac57fc0e6bf (glsl: Add isinf() and isnan() builtins) uses "+INF" in the .ir file to represent infinity. This worked on C99-compliant compilers, since the s-expression reader uses strtod() to read numbers, and C99 requires strtod() to understand "+INF". However, it didn't work on non-C99-compliant compilers such as MSVC. This patch modifies the s-expression reader to explicitly check for "+INF" rather than relying on strtod() to support it. This is a candidate for the 8.0 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44767 Tested-by: Morgan Armand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r600g: fix typo in evergreen registerAlex Deucher2012-01-191-7/+6
| | | | Signed-off-by: Alex Deucher <[email protected]>
* svga: move svga_texture() casts/calls in svga_surface_copy()Brian Paul2012-01-191-2/+4
| | | | | | | | | | | | | | To fix failed assertions when calling glCopyBufferSubData(). svga_texture() asserts that the resource is a texture. Simply move the calls to svga_texture() after the code that handles non-texture copies so that we don't call it with non-texture resources. Fixes glean bufferObject failure. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* st/mesa: copy num_immediates field when copying the immediates arrayBrian Paul2012-01-191-1/+5
| | | | | | | | | | | | | | | Two assignments to num_immediates were missing in get_pixel_transfer_visitor() and get_bitmap_visitor(). The uninitialized value led to valgrind errors and crashes in some cases. Added new assertions to catch future problems in this area. Also changed num_immediates to unsigned to avoid signed/unsigned comparison warnings. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* mesa: Set default access flags based on the run-time APIIan Romanick2012-01-196-18/+37
| | | | | | | | | | | | | | | | | | | The default access flags for OpenGL ES (via GL_OES_map_buffer) and desktop OpenGL are different. The code previously tried to handle this, but the decision was made at compile time. Since the same driver binary can be used for both OpenGL ES and desktop OpenGL, the decision must be made at run-time. This should fix bug #44433. It appears that the test case does various map and unmap operations and inspects the state of the buffer object around each. When it sees that GL_BUFFER_ACCESS does not match its expectations, it fails. NOTE: This is a candidate for release branches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44433
* st/mesa: add fallback pipe formats for (compressed) R, RG formatsBrian Paul2012-01-191-12/+22
| | | | | | | | | | | If we don't find an exact PIPE_FORMAT_x for a GL_(COMPRESSED)_RED/RG format, try uncompressed formats. We were already doing this for the RGB(A) formats. Fixes piglit arb_texture_compression-internal-format-query test. NOTE: This is a candidate for the stable branches. Reviewed-by: José Fonseca <[email protected]>
* i915g: Don't avoid flushing when we have a pending fence.Stéphane Marchesin2012-01-181-1/+4
| | | | | | | Otherwise the fence will never arrive. Also check for a NULL i915->batch. NOTE: This is a candidate for the 8.0 branch.
* i915g: Don't invert signalled/unsignalled fencesStéphane Marchesin2012-01-181-2/+2
| | | | NOTE: This is a candidate for the 8.0 branch.
* i965: Fix disassembly of data port writes on Ivybridge.Kenneth Graunke2012-01-181-1/+12
| | | | | | | | | | msg_type moved by a bit, so the message type was being disassembled incorrectly. In particular, render target writes were showing up as "OWORD block write". NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix disassembly of sampler messages on Ivybridge.Kenneth Graunke2012-01-181-1/+7
| | | | | | | | | Compared to sampler_gen5, simd_mode shifted by a bit and msg_type grew by a bit. So we were printing slightly incorrect numbers. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vs: Take attributes into account when deciding urb_entry_size.Kenneth Graunke2012-01-182-5/+8
| | | | | | | | | | | | | | | | | | | | Both the VF and VS share space in the URB. First, the VF stores attributes (shader inputs) there. The VS then reads the attributes, executes, and reuses the space to store varyings (shader outputs). Thus, we need to calculate the amount of URB space necessary for inputs, outputs, and pick whichever is greater. The old VS backend correctly did this (brw_vs_emit.c:408), but the new VS backend only considered outputs. Fixes vertex scrambling in GLBenchmark PRO on Ivybridge. NOTE: This is a candidate for the 8.0 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41318 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/dri: Remove useless flush front.Stéphane Marchesin2012-01-181-2/+7
| | | | | | | | | | | | | | | In the following scenario: - CreateContext C1 - MakeCurrent C1 - DestroyContext C1 (does not actually destroy the first context, postponed until the next MakeCurrent) - CreateContext C2 - MakeCurrent C2 MakeCurrent will call flush on a half destroyed context, leading to crashes. Since the other paths (destroy and makecurrent) already flush the context, there is no need to flush here, so we remove this useless flush front call. This fixes GPU crashes with Chrome and gallium drivers.
* intel: Set depth to 6 for cubemapsIan Romanick2012-01-182-5/+5
| | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41216 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43212 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43250 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Jin Yang <[email protected]>
* gbm: Validate usage flags in gbm_bo_create_from_egl_image()Kristian Høgsberg2012-01-184-4/+27
| | | | | The entry point is supposed to validate that the EGLImage is suitable for the passed in usage flags, but that was never implemented.
* i965: Add support for Z16 depth formats.Eric Anholt2012-01-181-0/+1
| | | | | | | | | | | | v2: Don't flag the format as being HiZ ready (there's DRI2 handshake pain to go through). Fixes piglit gl-3.0-required-sized-texture-formats NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Set up surface horizontal alignment field.Eric Anholt2012-01-181-1/+4
| | | | | | | | | | | | This is required for Z16 support for texturing, which is the first thing to have a horizontal alignment of 8. Renderbuffers don't need it, since they're always set up as the only mip level, but do it for completeness anyway. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Remove stale comment.Eric Anholt2012-01-181-1/+0
| | | | | | | | | This field is actually set up above. NOTE: This is a candidate for the 8.0 branch, to avoid conflicts. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* glsl: Fix leak of linked uniform names at relink/free of the shader_program.Eric Anholt2012-01-181-1/+1
| | | | NOTE: This is a candidate for the 8.0 branch.
* glsl: Fix leak of LinkedTransformFeedback.Varyings.Eric Anholt2012-01-181-1/+1
| | | | | | | | I copy-and-pasted the thing I was allocating for as the context, so the first time it would be NULL (root of a ralloc context) and they'd chain off each other from then on. NOTE: This is a candidate for the 8.0 branch.
* mesa: Fix leak of uniform storage records on shader program link/free.Eric Anholt2012-01-181-0/+2
| | | | NOTE: This is a candidate for the 8.0 branch.
* i965: Fix leak of the program cache BO on context destroy.Eric Anholt2012-01-181-0/+2
| | | | NOTE: This is a candidate for the 8.0 branch.
* i965/vs: Fix leak of an empty hash_table structure per compile.Eric Anholt2012-01-181-4/+0
| | | | | | | This statement got duplicated above, probably in a rebase resolution, so we never freed the extra one. NOTE: This is a candidate for the 8.0 branch.
* i965: Fix refcount leak of the gl_program structure.Eric Anholt2012-01-181-0/+2
| | | | | | | Fixes a leak of almost 200kb on a minimal shader_runner program (algebraic-add-add-1). NOTE: This is a candidate for the 8.0 branch.
* mesa: Make the register allocator allocation take a ralloc context.Eric Anholt2012-01-185-6/+12
| | | | | | This fixes a memory leak on i965 context destruction. NOTE: This is a candidate for the 8.0 branch.
* svga: change PIPE_CAPF_MAX_TEXTURE_LOD_BIAS from 16.0 to 15.0Brian Paul2012-01-181-1/+1
| | | | | | | | | The legal range for the device is apparently [-16.0, +15.0]. Limiting the range to [-15, +15] fixes piglit's lodbias test. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* svga: fix min/max lod clampingBrian Paul2012-01-181-4/+6
| | | | | | | | | | The interaction between the mipmap lod min/max limits and the texture base/max level limits is kind of tricky. Changing the base level didn't work as expected before. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* svga: add 0.5 in float->int conversion of sample min/max lodBrian Paul2012-01-181-2/+2
| | | | | | | | This makes lod clamping more consistent with other drivers. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* st/mesa: pass GL_MAP_INVALIDATE_RANGE_BIT to gallium driversBrian Paul2012-01-182-0/+4
| | | | | | when mapping renderbuffers or texture images. NOTE: This is a candidate for the 8.0 branch.
* mesa: use GL_MAP_INVALIDATE_RANGE_BIT in glTexImage pathsBrian Paul2012-01-182-3/+9
| | | | | | | | | | | | | Update the dd.h docs to indicate that GL_MAP_INVALIDATE_RANGE_BIT can be used with GL_MAP_WRITE_BIT when mapping renderbuffers and texture images. Pass the flag when mapping texture images for glTexImage, glTexSubImage, etc. It's up to drivers whether to actually make use of the flag. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Ian Romanick <[email protected]>
* mesa: try RGBA_FLOAT16 before RGBA_FLOAT32 when choosing A,L,LA,I formatsBrian Paul2012-01-181-0/+4
| | | | | | | | | To try to use less tex memory and maybe get better performance. Spotted by Roland Scheidegger. NOTE: This is a candidate for the 8.0 and 7.11 branches. Reviewed-by: José Fonseca <[email protected]>
* mesa: fix tex format selection for GL_R32F and other R/G float formatsBrian Paul2012-01-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | The i965 driver advertises GL_ARB_texture_float and GL_ARB_texture_rg support but the ctx->TextureFormatSupported[] table entries for MESA_FORMAT_R_FLOAT32 and MESA_FORMAT_RGBA_FLOAT32 are false on gen 4 hardware. So the case for GL_R32F would fail and we'd print an implementation error. This patch adds more Mesa tex format options for GL_R32F and other R/G formats so we fall back to 16-bit formats when 32-bit formats aren't available. Eric made the same fix in commit 6216a5b4 for the non R/G formats. v2: try 16-bit formats before 32-bit formats and try RG formats before RGBA where possible. This should fix https://bugs.freedesktop.org/show_bug.cgi?id=44039 NOTE: This is a candidate for the 8.0 and 7.11 branches. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600g: fix ISLT on r600/700Dave Airlie2012-01-181-1/+1
| | | | | | This fixes ISLT like evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r600g: make r600/700 use correct ineg.Dave Airlie2012-01-181-1/+1
| | | | | | Noticed by Vadim Girlin on irc. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix some of the interpolation tests.Dave Airlie2012-01-181-5/+10
| | | | | | | This enables linear gradients if we need a linear, it also sets the flat shade flag for color/constant interpolations. Signed-off-by: Dave Airlie <[email protected]>
* i965: Bump Ivybridge's fake MRF range to g112-127 instead of g111-126.Kenneth Graunke2012-01-181-1/+9
| | | | | | | | | | | | | | | | | | | | | When I originally implemented the hack to use GRFs 111+ as fake MRFs, I did so purely to avoid rewriting all the code that dealt with MRFs. However, it turns out that a similar hack is actually required. Newly discovered language in the BSpec indicates that SEND instructions with EOT set "should" use g112-g127 as their source registers. Based on assertions in the simulator, this is actually a requirement on certain platforms. Since we're faking MRFs already, we may as well use the officially sanctioned range. My guess is that we avoided this issue because we seldom use m0: URB writes in the new VS backend start at m1, and RT writes in the new FS backend start at m2. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove the INTEL_OLD_VS option.Kenneth Graunke2012-01-183-10/+3
| | | | | | | | | | | | | | | Now that we no longer generate Mesa IR from GLSL IR, it's impossible to use the old vertex shader backend for GLSL programs. There's simply no Mesa IR to codegen from. Any attempt to do so would result in immediate GPU hangs, presumably due to the driver uploading an empty program with no EOT message. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eugeni Dodonov <[email protected]>
* mesa: Support GL_VERTEX_ATTRIB_ARRAY_INTEGER in GL 3.0 contexts.Kenneth Graunke2012-01-181-1/+1
| | | | | | | | | According to Table 6.8 (Page 348) in the OpenGL 3.0 specification, glGetVertexAttribiv supports GL_VERTEX_ATTRIB_ARRAY_INTEGER. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kenneth Graunke <[email protected]>
* r600g: fix UINT_TO_FLT on evergreenVadim Girlin2012-01-181-1/+1
| | | | | | | It should be processed as trans-only. Signed-off-by: Vadim Girlin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/gen5: Fix rendering of depth buffers without stencil [v2]Chad Versace2012-01-171-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | Fixes the following OGLConform tests on gen5: depth-stencil(misc.state_on.depth_int) fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender) The problem was that, if the depth buffer's Mesa format was X8_Z24, then we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8 must be emitted. This bug was introduced by: commit d84a180417d1eabd680554970f1eaaa93abcd41e Author: Eric Anholt <[email protected]> i965: Base HW depth format setup based on MESA_FORMAT, not bpp. v2: Deref 'intel' directly. Move the branch for newer chipset to top. Quote the PRM. As requested by Ken. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408 Note: This is a candidate for the 8.0 branch. Reported-by: Xunx Fang <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Return if pointer to intel_context is nullAnuj Phogat2012-01-171-7/+7
| | | | | | | It is better to test if(intel == NULL) and simply return in that case. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* r600g: add workaround for original R600 PS setupAlex Deucher2012-01-171-2/+7
| | | | | | | | | The original R600 requires the UNCACHED_FIRST_INST bit to be set in the PS. Signed-off-by: Alex Deucher <[email protected]> Note: this is candidate for the stable branches.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 04:21:19 +0000