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* i965/sampler_state: Set the "Base Mip Level" field on Sandy BridgeJason Ekstrand2017-02-122-1/+20
* i965/sampler_state: Pass texObj into update_sampler_stateJason Ekstrand2017-02-121-6/+4
* i965/sampler_state: Clamp min/max LOD to 14 on gen7+Jason Ekstrand2017-02-121-2/+5
* st/mesa: don't pass compare mode for stencil-sampled texturesIlia Mirkin2017-02-121-1/+1
* nv50,nvc0: use alternate samplers for stencilIlia Mirkin2017-02-121-3/+3
* radv: Fix radv_GetPhysicalDeviceQueueFamilyProperties2KHR.Bas Nieuwenhuizen2017-02-131-9/+36
* etnaviv: Set shader instruction area correctly for GC3000Wladimir J. van der Laan2017-02-121-5/+21
* etnaviv: Update hw header filesWladimir J. van der Laan2017-02-125-48/+160
* radv: reduce CPU overhead merging bo lists.Dave Airlie2017-02-121-1/+11
* nvc0: set the render condition in the compute objectIlia Mirkin2017-02-111-2/+10
* gm107/ir: fix address offset bitfield for ATOMSIlia Mirkin2017-02-111-1/+1
* nv50/ir: convert an ATOM.EXCH without a destination into a storeIlia Mirkin2017-02-111-0/+5
* nvc0: fix 64-bit integer query buffer writesIlia Mirkin2017-02-113-20/+37
* nv50/ir: return a register when retrieving thread id sysvalIlia Mirkin2017-02-111-1/+1
* nv50/ir: add missing break after DSSGIlia Mirkin2017-02-111-0/+1
* etnaviv: shader-db tracesChristian Gmeiner2017-02-114-1/+47
* etnaviv: keep track of emitted loopsChristian Gmeiner2017-02-112-0/+7
* etnaviv: wire up core pipe_debug_callbackChristian Gmeiner2017-02-112-0/+15
* glsl: non-last member unsized array on SSBO must fail compilation on GLSL ES 3.1Jose Maria Casanova Crespo2017-02-101-4/+7
* vc4: Enable glSampleMask() even when !rasterizer->multisample.Eric Anholt2017-02-101-2/+1
* vc4: Respect glSampleMask() even when we're not writing color.Eric Anholt2017-02-101-3/+13
* vc4: Use the nir_builder helper for loading sample mask.Eric Anholt2017-02-101-10/+1
* vc4: Use accurate 1/w in coordinate shader as well as vert shader.Eric Anholt2017-02-101-1/+1
* vc4: Drop VS inputs to 8.Eric Anholt2017-02-101-4/+1
* vc4: Avoid emitting small immediates for UBO indirect load address guards.Eric Anholt2017-02-105-4/+20
* util/disk_cache: use stat() to check if entry is a directoryTimothy Arceri2017-02-101-9/+24
* st/nine: update configure options in the READMEEmil Velikov2017-02-101-2/+1
* loader: unconditionally include unistd.h and stdlib.hNicolai Hähnle2017-02-101-2/+2
* intel/blorp: do not return const data by get_px_size_sa()Emil Velikov2017-02-101-1/+1
* gallium/radeon: use staging for texture read mappings from GTT WCMarek Olšák2017-02-101-4/+5
* gallium/radeon: ignore the level parameter in buffer_transfer_mapMarek Olšák2017-02-101-5/+4
* gallium/radeon: fix performance of buffer readbacksMarek Olšák2017-02-101-8/+9
* radeonsi: align vertex buffer descriptor list size for optimal prefetchMarek Olšák2017-02-104-2/+7
* radeonsi: align shader binaries to CP DMA alignment for optimal prefetchMarek Olšák2017-02-101-1/+2
* radeonsi: move CP_DMA_ALIGNMENT definitionMarek Olšák2017-02-102-10/+10
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-103-6/+6
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-103-17/+8
* radeonsi: reduce the number of FMASK input coordinatesMarek Olšák2017-02-101-7/+3
* radeonsi: write shader asm annotated with wave info into GPU hang reportsMarek Olšák2017-02-103-3/+252
* radeonsi: write wave information into GPU hang reportsMarek Olšák2017-02-101-0/+20
* tgsi-dump: dump label if instruction has oneMarc-André Lureau2017-02-101-11/+13
* tgsi: remove ureg_label_insnMarc-André Lureau2017-02-102-38/+0
* radv: handle queue submission with no cs but semaphoresDave Airlie2017-02-091-2/+20
* util/disk_cache: error check asprintf()Timothy Arceri2017-02-101-5/+7
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nv50/ir: always return 0 when trying to read thread id along unit dimIlia Mirkin2017-02-094-5/+17
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0: increase number of ubo binding pointsIlia Mirkin2017-02-091-3/+2
* nvc0: expose int64Ilia Mirkin2017-02-091-1/+1
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
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