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* radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policyMarek Olšák2018-08-142-26/+41
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: declare coher in si_copy_bufferMarek Olšák2018-08-141-8/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: make PFP_SYNC_ME an explicit CP DMA flagMarek Olšák2018-08-141-17/+25
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in load_emitMarek Olšák2018-08-141-94/+37
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in store_emitMarek Olšák2018-08-141-92/+71
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in atomic_emitMarek Olšák2018-08-143-36/+47
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in build_interp_intrinsicMarek Olšák2018-08-141-19/+13
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline atomic_fetch_argsMarek Olšák2018-08-141-74/+51
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline store_fetch_argsMarek Olšák2018-08-141-61/+42
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline load_fetch_argsMarek Olšák2018-08-141-39/+28
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: merge txq_emit and resq_emitMarek Olšák2018-08-141-48/+45
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline resq_fetch_argsMarek Olšák2018-08-141-62/+34
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline txq_fetch_argsMarek Olšák2018-08-141-26/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: use get_resinfo directly in lower_gather4_integerMarek Olšák2018-08-141-13/+12
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline tex_fetch_args into build_tex_intrinsicMarek Olšák2018-08-141-222/+188
| | | | | | | The diff looks like it moves code that I didn't touch. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: remove fetch_args callbacks for ALU instructionsMarek Olšák2018-08-142-103/+55
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.cMarek Olšák2018-08-148-319/+348
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-148-2/+111
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_blitter: save/restore window rectanglesMarek Olšák2018-08-142-0/+29
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* noop: implement set_window_rectanglesMarek Olšák2018-08-141-0/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ddebug: implement set_window_rectanglesMarek Olšák2018-08-141-0/+12
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno/ir3: add support for a6xx 'merged' register setRob Clark2018-08-142-2/+24
| | | | | | | | | | Starting with a6xx, half and full precision registers conflict. Which makes things a bit more efficient, ie. if some parts of the shader are heavy on half-precision and others on full precision, you don't have to allocate the worst case for both. But it means we need to setup some additional conflicts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small RA cleanupRob Clark2018-08-142-13/+8
| | | | | | | Collapse is_temp() into it's only callsite, and pass compiler object as struct rather than void. Just cleanups to reduce noise in next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: stop hard-coding FS input regsRob Clark2018-08-147-183/+103
| | | | | | | | | | We originally did this because at the time we didn't know all the bitfields to configure where various frag shader sysval's went. But we do. So switch to using sysvals for all the frag shader inputs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use r63.x for unused inputsRob Clark2018-08-141-3/+3
| | | | | | | This way, unused sysval inputs, like frag_vcoord, get the correct regid value to disable the input. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: create all inputs in first blockRob Clark2018-08-141-17/+17
| | | | | | | | create_input()/create_input_compmask() should take the ctx as arg, rather than block, to enforce that all inputs are created in the first block, so that RA sees them as live at the start of the shader. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename s/frag_pos/frag_vcoord/gRob Clark2018-08-142-17/+22
| | | | | | | Make it more clear that this is varying fetch related. Also fixup some comments. Just cleanup for next patches. Signed-off-by: Rob Clark <[email protected]>
* compiler: add SYSTEM_VALUE_VARYING_COORDRob Clark2018-08-143-0/+8
| | | | | | | | Used internally in freedreno/ir3 for the vec2 value that hw passes to shader to use as coordinate for bary.f (varying fetch) instruction. This is not the same as SYSTEM_VALUE_FRAG_COORD. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move per-generation compiler configRob Clark2018-08-143-43/+52
| | | | | | | Move it from the compile ctx to the compiler object, before adding new things for a6xx. Signed-off-by: Rob Clark <[email protected]>
* radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.Bas Nieuwenhuizen2018-08-142-4/+5
| | | | | | | | | | | | | Behavior wrt firstInstance got changed, and a divisor of 0 has been disallowed. The new version of the ext got published in specification 1.1.81. Sending to stable since the only known user is DXVK, which needs this for correctness. Reviewed-by: Samuel Pitoiset <[email protected]> CC: 18.2 <[email protected]>
* radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.Bas Nieuwenhuizen2018-08-141-1/+2
| | | | | | | Follow radeonsi. Fixes: 3665f66ef26 "radv: Add support for ETC2 textures." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Fix missing Android platform define.Bas Nieuwenhuizen2018-08-142-1/+3
| | | | | CC: <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* freedreno: move free() into fdN_context_destroy()Rob Clark2018-08-145-2/+7
| | | | | | | | Following patches will be doing further cleanup after calling fd_context_destroy() so it is easier if we move the free() into the per-gen backend code. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: ir2 updateJonathan Marek2018-08-145-545/+615
| | | | | | | | | | | | | | | | | | | this patch brings a number of changes to ir2: -ir2 now generates CF clauses as necessary during assembly. this simplifies fd2_program/fd2_compiler and is necessary to implement optimization passes -ir2 now has separate vector/scalar instructions. this will make it easier to implementing scheduling of scalar+vector instructions together. dst_reg is also now seperate from src registers instead of a single list -ir2 now implements register allocation. this makes it possible to compile shaders which have more than 64 TGSI registers -ir2 now implements the following optimizations: removal of IN/OUT MOV instructions generated by TGSI and removal of unused instructions when some exports are disabled -ir2 now allows full 8-bit index for constants -ir2_alloc no longer allocates 4 times too many bytes Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* radv: Add on-demand compilation of built-in shaders.Bas Nieuwenhuizen2018-08-1413-80/+454
| | | | | | | | | | | | | | | | | | | | | | | | | In environments where we cannot cache, e.g. Android (no homedir), ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the startup cost of creating a device in radv is rather high, due to compiling all possible built-in pipelines up front. This meant depending on the CPU a 1-4 sec cost of creating a Device. For CTS this cost is unacceptable, and likely for starting random apps too. So if there is no cache, with this patch radv will compile shaders on demand. Once there is a cache from the first run, even if incomplete, the driver knows that it can likely write the cache and precompiles everything. Note that I did not switch the buffer and itob/btoi compute pipelines to on-demand, since you cannot really do anything in Vulkan without them and there are only a few. This reduces the CTS runtime for the no caches scenario on my threadripper from 32 minutes to 8 minutes. Reviewed-by: Dave Airlie <[email protected]>
* radv: Refactor blit pipeline creation.Bas Nieuwenhuizen2018-08-141-350/+175
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make fs key exemplars ordered to be a reverse fs_key lookup.Bas Nieuwenhuizen2018-08-147-88/+39
| | | | | | | While at it, share the exemplars and account for a non-occurring fs key. Reviewed-by: Dave Airlie <[email protected]>
* virgl: ARB_texture_barrier supportDave Airlie2018-08-146-3/+24
| | | | Reviewed-by: Tomeu Vizoso <[email protected]>
* mesa/glspirv: fix compilation with MSVCAlejandro Piñeiro2018-08-131-1/+1
| | | | | | | From AppVeyor #8582, it seems that MSVC doesn't like uint, so this patch replaces it with unsigned. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa/st/glsl_to_tgsi: fixup copy-paste mistakeErik Faye-Lund2018-08-131-1/+1
| | | | | | | | | | | | | This is clearly a copy-paste error; if we validate the reladdr2-pointer, we don't want to traverse to the reladdr-pointer. Especially since the check above shows that reladdr could be NULL here. Noticed by Coverity. CID: 1438389, 1438390 Fixes: 568bda2f2d3 ("mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly") Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gert Wollny <[email protected]>
* i965/nir: Use the nir copy of shader_info to handle gl_PatchVerticesInNeil Roberts2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | Instead of using the copy of shader_info stored in gl_program, it now uses the one in nir_shader. This is needed for SPIR-V because the info.tess.tcs_vertices_out is filled in via _mesa_spirv_to_nir which happens much later than with a GLSL shader. The copy of shader_data in gl_program is only updated later via brw_shader_gather_info but that is too late. For GLSL this shouldn't create any problems because the nir copy of the shader_info is immediately copied from the gl_program in glsl_to_nir. v2: updated after commit "i965: Combine both gl_PatchVerticesIn lowering passes." (488972) (Alejandro Piñeiro) Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: Set separate_shader on shader_infoNeil Roberts2018-08-131-0/+2
| | | | | | | | | The value is copied from the gl_program. If we don’t do this then it will get reset back to zero in brw_shader_gather_info. This isn’t a problem for GLSL because in that case the nir_shader is initialised with a copy of the shader_info from the gl_program. Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: pick off the only entry point we needIago Toral Quiroga2018-08-131-0/+15
| | | | | | | | | This is the same we do for vulkan drivers This is needed to pass the following CTS test: KHR-GL45.gl_spirv.spirv_modules_shader_binary_multiple_shader_objects_test Reviewed-by: Timothy Arceri <[email protected]>
* mesa/glspirv: compute double inputs and remap attributesAlejandro Piñeiro2018-08-131-0/+19
| | | | | | | | | | | | | | input locations used by input attributes are not handled in the same way in OpenGL vs Vulkan. There is a detailed explanation of such differences on the following commit: c2acf97fcc9b32eaa9778771282758e5652a8ad4 So with this commit, the same adjustment that is done after glsl_to_nir, is being done after spirv_to_nir, when it is used on OpenGL (ARB_gl_spirv). Reviewed-by: Timothy Arceri <[email protected]>
* nir/glsl: make nir_remap_attributes publicAlejandro Piñeiro2018-08-133-17/+27
| | | | | | As we plan to reuse it for ARB_gl_spirv implementation. Reviewed-by: Timothy Arceri <[email protected]>
* nir/lower_samplers: don't assume a deref for both texture and sampler srcsAlejandro Piñeiro2018-08-131-53/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit "nir: Use derefs in nir_lower_samplers" (75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both the texture and the sampler. However there are cases (on OpenGL, using ARB_gl_spirv) where SPIR-V is not providing a sampler, like for texture query levels ops. Although we could make spirv_to_nir to provide a sampler deref for those cases, it is not really needed, and wrong from the Vulkan point of view. This patch fixes the following (borrowed) tests run on SPIR-V mode: arb_compute_shader/execution/basic-texelFetch.shader_test arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test arb_texture_query_levels/execution/fs-baselevel.shader_test arb_texture_query_levels/execution/fs-maxlevel.shader_test arb_texture_query_levels/execution/fs-miptree.shader_test arb_texture_query_levels/execution/fs-nomips.shader_test arb_texture_query_levels/execution/vs-baselevel.shader_test arb_texture_query_levels/execution/vs-maxlevel.shader_test arb_texture_query_levels/execution/vs-miptree.shader_test arb_texture_query_levels/execution/vs-nomips.shader_test glsl-1.30/execution/fs-textureSize-compare.shader_test v2: merge lower_tex_src_to_offset and calc_sampler_offsets together, update texture/sampler index and texture_array_size directly on lower_tex_src_to_offset (Jason) v3: clarify one comment (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* nir/linker: take into account hidden uniformsAlejandro Piñeiro2018-08-132-1/+8
| | | | | | | | | | | | | | | | | | | | | So they are not exposed through the introspection API. It is worth to note that the number of hidden uniforms of GLSL linking vs SPIR-V linking would be somewhat different due the differen order of the nir lowerings/optimizations. For example: gl_FbWposYTransform. This is introduced as part of nir_lower_wpos_ytransform. On GLSL that is executed after the IR-based linking. So that means that on GLSL the UniformStorage will not include this uniform. With the SPIR-V linking, that uniform is already present, but marked as hidden. So it will be included on the UniformStorage, but as hidden. One alternative would create a special how_declared for that case, but seemed an overkill. Using hidden should be ok as far as it is used properly. Reviewed-by: Timothy Arceri <[email protected]>
* nir: add how_declared to nir_variable.dataAlejandro Piñeiro2018-08-133-1/+26
| | | | | | | | | Equivalent to the already existing how_declared at GLSL IR. The only difference is that we are not adding all the declaration_type available on GLSL, only the one that we will use on the short term. We would add more mode if needed on the future. Reviewed-by: Timothy Arceri <[email protected]>
* spirv: Make VertexIndex and VertexId both non-zero-basedNeil Roberts2018-08-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL has gl_VertexID which is supposed to be non-zero-based. SPIR-V has both VertexIndex and VertexId builtins whose meanings are defined by the APIs. Vulkan defines VertexIndex as being non-zero-based. In Vulkan VertexId and InstanceId have no meaning and are pretty much just reserved for OpenGL at this point. GL_ARB_spirv removes VertexIndex and defines VertexId to be the same as gl_VertexId (which is also non-zero-based). Previously in Mesa it was treating VertexIndex as non-zero-based and VertexId as zero-based, so it was breaking for GL. This behaviour was apparently based on Khronos bug 14255. However that bug doesn’t seem to have made a final decision for VertexId. Assuming there really is no other definition for VertexId for Vulkan it seems better to just make them both have the same value. v2: update comment and commit descriptions, based on Jason Ekstrand explanation of the meaning/rationale behind all those builtins (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: fill info.gs.input_primitive tooAlejandro Piñeiro2018-08-131-0/+2
| | | | | | | | | | | info.gs.output_primitive was already being filled. Not sure why this is not needed on Vulkan, but we found to be needed for ARB_gl_spirv. Specifically, this is needed to get the following test passing: KHR-GL45.gl_spirv.spirv_validation_builtin_variable_decorations_test Reviewed-by: Timothy Arceri <[email protected]>
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