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* nir/lower_alu_to_scalar: Use the builderJason Ekstrand2015-09-221-25/+22
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
| | | | | | | | | | | | | v2 (Ken): - Squash together commits for HS, DS, and TE, as well as fixes. - Add INTEL_MASK variants so we can use SET_FIELD if we want. - Rename GEN7_HS_INSTANCE_CONTROL to GEN7_HS_INSTANCE_COUNT to match the documentation. - Add some more fields from the PRMs. - Add Broadwell variants. Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* r600g: update num_dw in scissor_enable workaroundGrazvydas Ignotas2015-09-231-0/+1
| | | | | | | | | | "r600g: apply disable workaround on all scissors" forgot to update num_dw, fix it. Fixes: fbb423b433 "r600g: apply disable workaround on all scissors" Reported-and-tested-by: Markus Trippelsdorf <[email protected]> Signed-off-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/vec4: refactor brw_vec4_copy_propagation.Alejandro Piñeiro2015-09-221-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now it is more similar to brw_fs_copy_propagation, with three clear stages: 1) Build up the value we are propagating as if it were the source of a single MOV: 2) Check that we can propagate that value 3) Build the final value Previously everything was somewhat messed up, making the implementation on some specific cases, like knowing if you can propagate from a previous instruction even with type mismatches, even messier (for example, with the need of maintaining more of one has_source_modifiers). The refactoring clears stuff, and gives support to this mentioned use case without doing anything extra (for example, only one has_source_modifiers is used). Shader-db results for vec4 programs on Haswell: total instructions in shared programs: 1683842 -> 1669037 (-0.88%) instructions in affected programs: 739837 -> 725032 (-2.00%) helped: 6237 HURT: 0 v2: using 'arg' index to get the from inst was wrong v3: rebased against last change on the previous patch of the series v4: don't need to track instructions on struct copy_entry, as we only set the source on a direct copy v5: change the approach for a refactoring v6: tweaked comments Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa: remove st_bind_framebuffer()Brian Paul2015-09-221-12/+0
| | | | | | | The function was a no-op and if the ctx->Driver.BindFramebuffer pointer is null, Mesa won't try to use it. Reviewed-by: Matt Turner <[email protected]>
* mesa: const-qualify _mesa_is_legal_tex_storage_format ctx paramBrian Paul2015-09-222-2/+4
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: const-qualify _mesa_base_tex_format() ctx paramBrian Paul2015-09-222-2/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: const-qualify buffer_object_subdata_range_good() bufObj parameterBrian Paul2015-09-221-1/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: whitespace, comment fixes in texstorage.cBrian Paul2015-09-221-15/+18
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* mesa/es3.1: Enable GL_ARB_vertex_attrib_binding functionality for GLES 3.1Marta Lofstedt2015-09-221-7/+7
| | | | Signed-off-by: Marta Lofstedt <[email protected]>
* mesa/es3.1: Allow query of Vertex bindings for GLES 3.1Marta Lofstedt2015-09-221-3/+4
| | | | Signed-off-by: Marta Lofstedt <[email protected]>
* mesa/es3.1 : Align OpenGL ES 3.1 glBindVertexBuffer error handling with ↵Marta Lofstedt2015-09-221-1/+1
| | | | | | | | | | | | OpenGL Core According to OpenGL ES 3.1 specification 10.3.1: "An INVALID_OPERATION error is generated if buffer is not zero or a name returned from a previous call to GenBuffers, or if such a name has since been deleted with DeleteBuffers." This error check was previously limited to OpenGL Core. Signed-off-by: Marta Lofstedt <[email protected]>
* i965: fix textureGrad for cubemapsTapani Pälli2015-09-221-19/+182
| | | | | | | | | | | | | | | | | | | Fixes bugs exposed by commit 2b1cdb0eddb73f62e4848d4b64840067f1f70865 in: ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_frag No regressions observed in deqp, CTS or Piglit. v2: address review feedback from Iago Toral: - move rho calculation to else branch - optimize dx and dy calculation - fix documentation inconsistensies Signed-off-by: Tapani Pälli <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91114 Cc: "10.6 11.0" <[email protected]>
* nir: Report progress from nir_normalize_cubemap_coords().Kenneth Graunke2015-09-212-8/+23
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add braces around multi-line loop.Kenneth Graunke2015-09-211-1/+2
| | | | | | | This was correct but not our usual style. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from nir_lower_system_values().Kenneth Graunke2015-09-212-10/+19
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from nir_split_var_copies().Kenneth Graunke2015-09-212-4/+13
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from nir_lower_locals_to_regs().Kenneth Graunke2015-09-212-4/+16
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from nir_remove_dead_variables().Kenneth Graunke2015-09-212-5/+12
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from lower_vec_to_movs().Jason Ekstrand2015-09-212-7/+22
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Report progress from nir_lower_globals_vars_to_local().Kenneth Graunke2015-09-212-2/+6
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Clean up GLSL compiler option setupJason Ekstrand2015-09-211-26/+20
| | | | | | | | | The only functional change here is that we now set EmitNoIndirectOutput and EmitNoIndirectTemp for compute shaders. Compute shaders don't have outputs per-se and we should have been setting EmitNoIndirectTemp all along. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Use larger URB size where available.Ben Widawsky2015-09-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | All SKL SKUs except the lowest one which has half the L3 size actually have 384K of URB per slice. For once, I can explain how this mistake was made and how it was missed in review... Historically when we enable a platform and put the production sizes, you can simply look at the "smallest" SKU and see what its URB size is (and we assumed it was the 1 slice variant). Since on newer platforms the URB sizes are scaled automatically by HW, this was sufficient. On SKL, this is a bit different as the lowest SKU actually has half of the L3 fused off. GT2 is the 1 slice (not GT1) variant and it has 384K. There are no Jenkins tests fixed (or regressions) and we don't expect any fixes here because you can always run with less URB size. Thanks to Sarah for bringing this to my attention. Cc: Sarah Sharp <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir/builder: Don't use designated initializersJason Ekstrand2015-09-211-3/+18
| | | | | | | | | | | Designated initializers are not allowed in C++ (not even C++11). Since nir_lower_samplers is now using nir_builder, and nir_lower_samplers is in C++, this breaks the build on some compilers. Aparently, GCC 5 allows it in some limited extent because mesa still builds on my system without this patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92052 Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Move system value -> intrinsic mapping into nir.cJason Ekstrand2015-09-213-40/+40
| | | | | | This way they're right next to the map going the other direction. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: rename nir_lower_samplers.c{pp,}Emil Velikov2015-09-212-5/+3
| | | | | | | | | | | | | | | | | | With the only C++ function having its own wrapper we can 'demote' this file to a normal C one. This allows us to get rid of extern C { #include <foo.h> } 'hacks'. Plus some of the headers may use C99 initializers, which are not supported by the ISO standard. This may cause build issue on incremental builds. If so run the following: sed -i -e 's|samplers\.cpp|samplers.c|' src/glsl/nir/.deps/nir_lower_samplers.Plo Fixes: ef8eebc6ad5(nir: support indirect indexing samplers in struct arrays) Signed-off-by: Emil Velikov <[email protected]> Reported-by: Gottfried Haider <[email protected]> Tested-by: Gottfried Haider <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nir: add C wrapper around glsl_type::record_location_offsetEmil Velikov2015-09-212-0/+9
| | | | | | | | This will allow us to convert nir_lower_sampler.cpp to C. Signed-off-by: Emil Velikov <[email protected]> Tested-by: Gottfried Haider <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nir: move stdio.h inclusion before extern CEmil Velikov2015-09-211-2/+2
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Tested-by: Gottfried Haider <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Fix MRF register number assertions for compr4.Kenneth Graunke2015-09-211-2/+2
| | | | | | | | | | compr4 is represented by setting the high bit on the MRF number. We need to mask it out before sanity checking the register number. Fixes ~8000 assert fails on Ironlake and G45. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92066 Signed-off-by: Kenneth Graunke <[email protected]>
* radeonsi: implement TXQS supportIlia Mirkin2015-09-212-25/+69
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Fredrik Bruhn <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: load fmask ptr relative to the resources arrayIlia Mirkin2015-09-211-1/+1
| | | | | | | | | | | res_ptr already contains the resource values. fmask_ptr needs to be looked up relative to the start of the resource params. Note that this only affects indirect loads of MS sampler arrays. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]>
* i965/vec4: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-218-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some bug reports about shaders failing to compile in gen6 because MRF 14 is used when we need to spill. For example: https://bugs.freedesktop.org/show_bug.cgi?id=86469 https://bugs.freedesktop.org/show_bug.cgi?id=90631 Discussion in bugzilla pointed to the fact that gen6 might actually have 24 MRF registers available instead of 16, so we could use other MRF registers and avoid these conflicts (we still need to investigate why some shaders need up to MRF 14 anyway, since this is not expected). Notice that the hardware docs are not clear about this fact: SNB PRM Vol4 Part2's "Table 5-4. MRF Registers Available in Device Hardware" says "Number per Thread" - "24 registers" However, SNB PRM Vol4 Part1, 1.6.1 Message Register File (MRF) says: "Normal threads should construct their messages in m1..m15. (...) Regardless of actual hardware implementation, the thread should not assume th at MRF addresses above m15 wrap to legal MRF registers." Therefore experimentation was necessary to evaluate if we had these extra MRF registers available or not. This was tested in gen6 using MRF registers 21..23 for spilling and doing a full piglit run (all.py) forcing spilling of everything on the FS backend. It was also tested by doing spilling of everything on both the FS and the VS backends with a piglit run of shader.py. In both cases no regressions were observed. In fact, many of these tests where helped in the cases where we forced spilling, since that triggered the same underlying problem described in the bug reports. Here are some results using INTEL_DEBUG=spill_fs,spill_vec4 for a shader.py run on gen6 hardware: Using MRFs 13..15 for spilling: crash: 2, fail: 113, pass: 6621, skip: 5461 Using MRFs 21..23 for spilling: crash: 2, fail: 12, pass: 6722, skip: 5461 This patch sets the ground for later patches to implement spilling using MRF registers 21..23 in gen6. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-214-7/+16
| | | | | | | | | | | | | | | In a later patch we will make BRW_MAX_MRF return a different value depending on the hardware generation, but it is inconvenient to add a gen parameter to the brw_reg functions only for the assertions, so move these to places where we have the hardware generation available. Ken suggested to add the asserts to brw_set_src0 and brw_set_dest since that would make sure that we catch all uses of MRF registers, even those coming from modules that generate native code directly, like blorp. Unfortunately, this is very late in the process which can make things harder to debug, so add asserts to the generator as well. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-09-214-2/+10
| | | | | | | | | | | | | | | | | | | Until now we only used MRFs 1..15 for regular SEND messages, so the message length could not possibly exceed the maximum size. Soon we'll allow to use MRF registers 1..23 in gen6, so we need to be careful not to build messages that can go beyond the limit. That could occur, specifically, when building URB write messages, which we may need to split in chunks due to their size. Previously we would simply go and create a new message when we reached MRF 13 (since 13..15 were reserved for spilling), now we also want to check the size of the message explicitly. Besides adding that condition to split URB write messages properly, this patch also adds asserts in the generator. Notice that brw_inst_set_mlen already asserts for this, but asserting in the generators is easy and can make debugging easier in some cases. Reviewed-by: Kenneth Graunke <[email protected]>
* nir/print: fix coverity errorRob Clark2015-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Not something actually hit in real life (now state is never non-null, but only case state->syms is null is if nir_print_instr() path). But it was something I overlooked the first time, so might as well fix it. *** CID 1324642: Null pointer dereferences (REVERSE_INULL) /src/glsl/nir/nir_print.c: 299 in print_var_decl() 293 294 fprintf(fp, " (%s, %u)", loc, var->data.driver_location); 295 } 296 297 fprintf(fp, "\n"); 298 >>> CID 1324642: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "state" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 299 if (state) { 300 _mesa_set_add(state->syms, name); 301 _mesa_hash_table_insert(state->ht, var, name); 302 } 303 } 304 Signed-off-by: Rob Clark <[email protected]>
* i965/vec4/nir: Remove all "this->" snippetsEduardo Lima Mitev2015-09-201-16/+15
| | | | | | | | For consistency, either we have all class members dereferenced, or none. In this case, very few are so lets get rid of them all. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri/common: fix gbm-symbols-check regressionMarcin Ślusarz2015-09-201-1/+1
| | | | | | | | Broken by commit c228514c72cb2fd5fb9e510808e29204fc9e7ae1 "dri/common: use sysconfdir when looking for drirc". Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92054 Signed-off-by: Marcin Ślusarz <[email protected]>
* mesa/teximage: reuse compressed format utility functions for base_formatNanley Chery2015-09-191-145/+5
| | | | | | | | | | | | | | | Reuse utility functions instead of reimplementing the same logic. * _mesa_is_compressed_format() performs the required checking to determine format support in the current context. * _mesa_gl_compressed_format_base_format() returns the base format. As a side effect, we now check that we're in a desktop context when determining support for the FXT1 and RGTC formats. This is in agreement with our extension table and the glext headers. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/texcompress: add compressed formats to base format utility functionNanley Chery2015-09-191-0/+14
| | | | | | | Add S3TC and PALETTE formats. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/glformats: refactor compressed format support functionNanley Chery2015-09-191-79/+40
| | | | | | | | | | | Instead of case statements, use _mesa_get_format_layout() to determine if a GL format is part of a family of compressed formats. v2. restrict LATC formats to API_OPENGL_COMPAT (Ilia). rename the variable mFormat to m_format. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/formats: add MESA_LAYOUT_LATCNanley Chery2015-09-195-16/+7
| | | | | | | | | This enables us to predicate statments on a compressed format being a type of LATC format. Also, remove the comment that lists the enum (it was getting a tad long). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* dri/common: use sysconfdir when looking for drircMarcin Ślusarz2015-09-192-1/+6
| | | | | | | | Useful when locally installed mesa has more quirks than the system one. Signed-off-by: Marcin Ślusarz <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* freedreno/ir3: use nir two-sided-color loweringRob Clark2015-09-181-21/+3
| | | | | | | | With this, we completely switch over to nir lowering passes instead of tgsi_lowering. So one step closer to supporting direct glsl or spirv to nir support for freedreno a3xx/a4xx. Signed-off-by: Rob Clark <[email protected]>
* nir: add two-sided-color lowering passRob Clark2015-09-183-0/+211
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/build: add nir_vec() helperRob Clark2015-09-183-31/+20
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* freedreno/ir3: lower txp/clamp in NIRRob Clark2015-09-181-26/+30
| | | | Signed-off-by: Rob Clark <[email protected]>
* nir/lower_tex: add support to clamp texture coordsRob Clark2015-09-182-1/+103
| | | | | | | | | | | | | | Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the shader to emulate GL_CLAMP. This is added to lower_tex_proj since, in the case of projected coords, the clamping needs to happen *after* projection. v2: comments/suggestions from Ilia and Eric, use txs to get texture size and clamp RECT textures to their dimensions rather than [0.0, 1.0] to avoid having to lower RECT textures to 2D. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/lower_tex: support for lowering RECT texturesRob Clark2015-09-182-3/+63
| | | | | | | | v2: comments/suggestions from Ilia and Eric, split out get_texture_size() helper so we can use it in the next commit for clamping RECT textures. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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