summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* st/mesa: undo a couple static assertsBrian Paul2012-07-271-2/+2
| | | | Hmm, gcc didn't catch these mistakes, but MSVC did.
* st/mesa: use STATIC_ASSERT in a few placesBrian Paul2012-07-274-17/+17
|
* mesa: whitespace, etc. fixes in program.hBrian Paul2012-07-271-7/+5
|
* meta: fix glDrawPixels fallback test, stencil drawingBrian Paul2012-07-271-2/+2
| | | | | | | | | | | | | | | | | | Remove the check for pixel transfer ops. If any RGB/depth scale/bias is in effect, it'll be applied in the glTexImage step. If drawing stencil pixels we need to disable pixel transfer so that alpha scale/bias are not applied to the stencil data. These issues were spotted by Roland. Fixes Blender performance issues reported in http://bugs.freedesktop.org/show_bug.cgi?id=47375 NOTE: This is a candidate for the 8.0 branch. Tested-by: Barto <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeon: fix 'sowftware' typoBrian Paul2012-07-271-1/+1
|
* i965/gen7: Reduce GT1 WM thread count according to updated BSpec.Eric Anholt2012-07-271-1/+1
| | | | | | Acked-by: Kenneth Graunke <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=52382
* i965: Fix typo in shader channel select field name.Kenneth Graunke2012-07-273-20/+20
| | | | | | "chanel" isn't very searchable. I can type, honest! Signed-off-by: Kenneth Graunke <[email protected]>
* i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.Paul Berry2012-07-271-1/+1
| | | | | | | | | | | | No functional change. This patch modifies intel_miptree_alloc_mcs to allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of MESA_FORMAT_A8. In principle it doesn't matter, since we only access the buffer using MCS-specific hardware mechanisms, so all that's important is to use a format with the correct size. However, MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to avoid it. Acked-by: Kenneth Graunke <[email protected]>
* intel: increase wm thread number to 80 on gen6 GT2Zou Nan hai2012-07-271-5/+1
| | | | | | | | | | | | | It seems reset is not required for setting the max_wm_threads to 80 on gen6 GT2. Increases performance in the Counter-Strike: Source video stress test by 7.18% (n=5). Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Matt Turner <[email protected]> Acked-by: Eric Anholt <[email protected]>
* r600g: Emit dispatch state for compute directly to the csTom Stellard2012-07-274-69/+60
| | | | | | | We no longer rely on an evergreen_compute_resource for emitting dispatch state. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atomTom Stellard2012-07-271-2/+5
| | | | | | | The value of this register will always be DI_PT_POINTLIST for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Atomize compute shader stateTom Stellard2012-07-274-86/+91
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add helper functions for emitting compute SET_CONTEXT packetsTom Stellard2012-07-272-5/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
|
* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
|
* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
|
* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
| | | | | These are needed for correctly lowering branch instructions in some cases.
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
|
* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
| | | | | | | The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa.
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
|
* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
|
* radeonsi: Enable PIPE_SHADER_CAP_INTEGERSTom Stellard2012-07-271-1/+2
|
* radeonsi: Add support for loading integers from constant memoryTom Stellard2012-07-271-1/+3
|
* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
|
* radeon/llvm: Add custom lowering for SELECT_CC nodes on SITom Stellard2012-07-272-0/+20
|
* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-272-41/+41
|
* radeon/llvm: Implement getSetCCResultType for SITom Stellard2012-07-272-0/+6
|
* radeon/llvm: Custom lower BR_CC for SITom Stellard2012-07-272-0/+41
|
* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-274-31/+31
| | | | | SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-274-38/+29
| | | | | SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
|
* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-274-111/+112
| | | | | SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector.
* automake: Remove OPT_FLAGS.Eric Anholt2012-07-262-2/+0
| | | | | | | | | | If you want to change your compiler arguments, just set CFLAGS/CXXFLAGS. Having Mesa have this separate variable is a great way to have your arguments not thoroughly propagated to all compiler invocations. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Remove ARCH_FLAGS.Eric Anholt2012-07-262-2/+0
| | | | | | | | | | In all current uses, it was appended to CFLAGS, which already had -m32. If you want to do some other flag supplied to compiler invocations, there's CFLAGS/CXXFLAGS. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: use ROUND_DOWN_TO macro.Paul Berry2012-07-261-6/+6
| | | | | | | | No functional change. This patch modifies brw_blorp_blit.cpp to use the ROUND_DOWN_TO macro instead of open-coded bit manipulations, for clarity. Reviewed-by: Kenneth Graunke <[email protected]>
* svga: initialize svga_compile_key to zeros to be safeBrian Paul2012-07-261-0/+4
|
* svga: fix invalid memory reference in needs_to_create_zero()Brian Paul2012-07-261-5/+5
| | | | | | | | | | | | | | The emit->key.fkey info is only valid if we're generating a fragment shader. We should not look at it if we're generating a vertex shader. When generating a vertex shader, the value of emit->key.fkey.num_textures was garbage and the loop over num_textures would read invalid data. At best this would cause us to emit an unused constant. At worse, we could segfault. Just by dumb luck, fkey.num_textures was usually a smallish integer. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
* radeon: fix Base/base typoBrian Paul2012-07-261-1/+1
| | | | Fixes http://bugs.freedesktop.org/show_bug.cgi?id=52563
* android-build: fix dricore build for autogenerated files (v3)Daniel Charles2012-07-265-299/+335
| | | | | | | | | | | | | | | | | | | | | | | | Recently more files were removed from control to be auto-generated in the dricore library. Android build was not able to locate the new files if they were not created beforehand. LOCAL_SRC_FILES includes some of those files and Android.gen.mk re-defines this variable by filtering out the auto-generated files. Unfortunately for this variable it is not the same to have the SRCDIR variable defined as the current directory. By re-defining SRCDIR for the autotools build the Android build system is happy again and the new files were actually removed from the sources to use the auto generated versions. Also patch d5c1801a018efda8ac2b was partially reverted as the files can not be compiled to the LOCAL_PATH, instead they should live on the intermediates folder so that a clean can wipe them out. v3: [chad] Fix the definition of SRCDIR in libdricore/Makefile.am. Signed-off-by: Chad Versace <[email protected]> Signed-off-by: Daniel Charles <[email protected]>
* radeon: set swrast_renderbuffer::ColorType field when mapping renderbuffersBrian Paul2012-07-261-0/+2
| | | | | | | | Fixes http://bugs.freedesktop.org/show_bug.cgi?id=47375 NOTE: This is a candidate for the 8.0 branch. Tested-by: Barto <[email protected]>
* xlib: add X error handler around XGetImage() callBrian Paul2012-07-261-0/+29
| | | | | | | | | | XGetImage() will generate a BadMatch error if the source window isn't visible. When that happens, create a new XImage. Fixes piglit 'select' test failures with swrast/xlib driver. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove obsolete matrix commentBrian Paul2012-07-261-1/+0
|
* mesa: fix comment typo: s/pointer/point/Brian Paul2012-07-261-1/+1
|
* mesa: remove _math_matrix_alloc_inv()Brian Paul2012-07-264-48/+13
| | | | | | | Always allocate space for the inverse matrix in _math_matrix_ctr() since we were always calling _math_matrix_alloc_inv() anyway. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: loosen small matrix determinant checkBrian Paul2012-07-261-1/+1
| | | | | | | | | | | | | When computing a matrix inverse, if the determinant is too small we could hit a divide by zero. There's a check to prevent this (we basically give up on computing the inverse and return the identity matrix.) This patch loosens this test to fix a lighting bug reported by Lars Henning Wendt. v2: use abs(det) to handle negative values NOTE: This is a candidate for the 8.0 branch. Tested-by: Lars Henning Wendt <[email protected]>
* i965: Use sendc for all render target writes on Gen6+.Paul Berry2012-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The sendc instruction causes the fragment shader thread to wait for any dependent threads (i.e. threads rendering to overlapping pixels) to complete before sending the message. We need to use sendc on the first render target write in order to guarantee that fragment shader outputs are written to the render target in the correct order. Previously, we only used the "sendc" instruction when writing to binding table index 0. This did the right thing for fragment shaders, because our fragment shader back-ends always issue their first render target write to binding table index 0. However, it did the wrong thing for blorp, which performs its render target writes to binding table index 1. A more robust solution is to use sendc for all render target writes. This should not produce any performance penalty, since after the first sendc, all of the dependent threads will have completed. For more information about sendc, see the Ivy Bridge PRM, Vol4 Part3 p218 (sendc - Conditional Send Message), and p54 (TDR Registers). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/msaa: Remove TODO comments that are no longer relevant.Paul Berry2012-07-262-3/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Make more consistent use of _mesa_is_{user,winsys}_fbo()Paul Berry2012-07-269-12/+19
| | | | | | | | | | A lot of code was still differentiating between between winsys and user fbos by testing the fbo's name against zero. This converts everything in the i915 and 965 drivers over to use _mesa_is_user_fbo() and _mesa_is_winsys_fbo(). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make more consistent use of _mesa_is_{user,winsys}_fbo()Paul Berry2012-07-268-13/+23
| | | | | | | | | | A lot of code was still differentiating between between winsys and user fbos by testing the fbo's name against zero. This converts everything in core mesa, the state tracker, and src/mesa/program over to use _mesa_is_user_fbo() and _mesa_is_winsys_fbo(). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: warning: pragma `invariant(all)' not supported in GLSL ES 1.00Oliver McFadden2012-07-261-1/+1
| | | | | | | | | | | | The OpenGL(R) ES Shading Language Version 1.00 Revision 17 (12 May, 2009) > 4.6.1 The Invariant Qualifier > ... To force all output variables to be invariant, use the pragma > #pragma STDGL invariant(all) Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 06:01:36 +0000