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* glsl: Bitwise conversion operator support in ir_validate.Olivier Galibert2012-06-071-0/+16
| | | | | Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Bitwise conversion operator support in ir_expression.Olivier Galibert2012-06-071-0/+4
| | | | | Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: New unary opcodes for ARB_shader_bit_encoding support.Olivier Galibert2012-06-077-11/+125
| | | | | | | The opcodes are bitcast_f2u, bitcast_f2i, bitcast_i2f and bitcast_u2f. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Scaffolding for ARB_shader_bit_encoding.Olivier Galibert2012-06-078-0/+11
| | | | | | | | That adds support for activating the extension. It doesn't actually *do* anything yet, of course. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Return 8 bits for GL_TEXTURE_RED_SIZE on RGTC formats.Kenneth Graunke2012-06-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | From the issues section of the GL_ARB_texture_compression_rgtc extension: 15) What should glGetTexLevelParameter return for GL_TEXTURE_GREEN_SIZE and GL_TEXTURE_BLUE_SIZE for the RGTC1 formats? What should glGetTexLevelParameter return for GL_TEXTURE_BLUE_SIZE for the RGTC2 formats? RESOLVED: Zero bits. These formats always return 0.0 for these respective components and have no bits devoted to these components. Returning 8 bits for red size of RGTC1 and the red and green sizes of RGTC2 makes sense because that's the maximum potential precision for the uncompressed texels. Thus, we need to return 8 bits for GL_TEXTURE_RED_SIZE on all RGTC formats and 8 bits for GL_TEXTURE_GREEN_SIZE on RGTC2 formats. BLUE should be 0. Fixes oglconform/rgtc/advanced.texture_fetch.tex_param. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl: Hook up loop_variable_state destructor to plug a memory leak.Kenneth Graunke2012-06-071-0/+17
| | | | | | | | | | | | | While ~loop_state() is already freeing the loop_variable_state objects via ralloc_free(this->mem_ctx), the ~loop_variable_state() destructor was never getting called, so the hash table inside loop_variable_state was never getting destroyed. Fixes a memory leak in any shader with loops. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]>
* radeon/llvm: Emulate RECIP_UINT instruction on CaymanTom Stellard2012-06-062-4/+13
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* radeon/llvm: Remove some duplicate code in the R600 CodeEmitterTom Stellard2012-06-061-9/+3
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* radeon/llvm: Fix MULLO* instructions on CaymanTom Stellard2012-06-064-14/+53
| | | | | On Cayman, the MULLO* instructions must fill all slots in an instruction group.
* r600g: Compute support for CaymanTom Stellard2012-06-065-66/+95
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* xorg: port to new compat API.Dave Airlie2012-06-068-63/+162
| | | | Signed-off-by: Dave Airlie <[email protected]>
* mesa: consolidate internal glCompressedTexSubImage1/2/3D codeBrian Paul2012-06-067-138/+42
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glCompressedTexImage1/2/3D codeBrian Paul2012-06-067-140/+44
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glCopyTexSubImage1/2/3D codeBrian Paul2012-06-0610-220/+62
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glTexSubImage1/2/3D codeBrian Paul2012-06-0610-195/+61
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glTexImage1/2/3D codeBrian Paul2012-06-0610-343/+73
| | | | | | | The functions for handling 1D, 2D and 3D texture images were nearly identical. This folds them all together. Reviewed-by: Kenneth Graunke <[email protected]>
* translate_test: add support for half floatsBrian Paul2012-06-061-0/+8
| | | | | | Fixes assertion reported in https://bugs.freedesktop.org/show_bug.cgi?id=44519 but there's still failing cases.
* radeon/llvm: Remove obselete hooks for the ConvertToISA passTom Stellard2012-06-066-87/+1
| | | | | | We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more.
* radeon/llvm: Remove AMDIL MOVE* instructionsTom Stellard2012-06-065-20/+2
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* radeon/llvm: Add isMov() to AMDILInstrInfoTom Stellard2012-06-066-11/+34
| | | | | This enables the CFGStructurizer to work without the AMDIL::MOV* instructions.
* radeon/llvm: Remove deadcode from the AMDILISelLowering classTom Stellard2012-06-062-203/+0
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* radeon/llvm: Don't lower RETURN to S_ENDPGM on SITom Stellard2012-06-062-1/+4
| | | | | Instead create an S_ENDPGM instruction in the CodeEmitter and emit it after all the other instructions.
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-068-97/+12
| | | | This obsoletes the AMDGPULowerInstruction pass.
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-0613-322/+33
| | | | This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
* nouveau: fix scratch buffer leakMarcin Slusarz2012-06-054-3/+15
| | | | ...and create common function for destroying nouveau_context
* nv50: fix nv50_stream_output_state leakMarcin Slusarz2012-06-051-0/+3
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* nv50: fix symbol table memory leakMarcin Slusarz2012-06-051-0/+3
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* i965/fs: Fix user-defined FS outputs with less than four components.Kenneth Graunke2012-06-052-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OpenGL allows you to declare user-defined fragment shader outputs with less than four components: out ivec2 color; This makes sense if you're rendering to an RG format render target. Previously, we assumed that all color outputs had four components (like the built-in gl_FragColor/gl_FragData variables). This caused us to call emit_color_write for invalid indices, incrementing the output virtual GRF's reg_offset beyond the size of the register. This caused cascading failures: split_virtual_grfs would allocate new size-1 registers based on the virtual GRF size, but then proceed to rewrite the out-of-bounds accesses assuming that it had allocated enough new (contiguously numbered) registers. This resulted in instructions that accessed size-1 GRFs which register numbers beyond virtual_grf_next (i.e. registers that were never allocated). Finally, this manifested as live variable analysis and instruction scheduling accessing their temporary array with an out of bounds index (as they're all sized based on virtual_grf_next), and the program would segfault. It looks like the hardware's Render Target Write message requires you to send four components, even for RT formats such as RG or RGB. This patch continues to use all four MRFs, but doesn't bother to fill any data for the last few, which should be unused. +2 oglconforms. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Fix texelFetchOffset() on pre-Gen7.Kenneth Graunke2012-06-051-2/+2
| | | | | | | | | | | Commit 4650aea7a536ddce120576fadb91845076e8e37a fixed texelFetchOffset() on Ivybridge, but didn't update the Ironlake/Sandybridge code. +18 piglits on Sandybridge. NOTE: This and 4650aea7a536ddce are both candidates for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix texelFetchOffset() on pre-Gen7.Kenneth Graunke2012-06-051-12/+28
| | | | | | | | | | | Commit f41ecade7b458c02d504158b522acb2231585040 fixed texelFetchOffset() on Ivybridge, but didn't update the Ironlake/Sandybridge code. +15 piglits on Sandybridge. NOTE: This and f41ecade7b458 are both candidates for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* meta: Fix GL_RENDERBUFFER binding in decompress_texture_image().Kenneth Graunke2012-06-051-0/+4
| | | | | | | | | | | | | This isn't saved/restored by _mesa_meta_begin, so we need to do it manually (like we do for the read/draw framebuffers). Additionally, we neglected to re-bind before the glRenderbufferStorage call. +13 oglconforms. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Unbind ARB_transform_feedback2 binding points on Delete too.Kenneth Graunke2012-06-051-1/+7
| | | | | | | | | | | | DeleteBuffer needs to unbind from these binding points as well, based on the same rationale as the previous patch. +51 oglconforms (together with the last patch). NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Support BindBuffer{Base,Offset,Range} with a buffer of 0.Kenneth Graunke2012-06-051-3/+18
| | | | | | | | | | | | | _mesa_lookup_bufferobj returns NULL for 0, which caused us to say "there's no such buffer object" and raise an error, rather than correctly binding the shared NullBufferObj. Now you can unbind your buffers. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Unbind ARB_copy_buffer and transform feedback buffers on delete.Kenneth Graunke2012-06-051-0/+13
| | | | | | | | | | | | | | | | | According to the GL 3.1 spec, section 2.9 ("Buffer Objects"): "If a buffer object is deleted while it is bound, all bindings to that object in the current context (i.e. in the thread that called DeleteBuffers) are reset to zero." The code already checked for a number of cases, but neglected these newer binding points. +21 oglconforms. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl/builtins: Fix textureGrad() for Array samplers.Kenneth Graunke2012-06-051-3/+3
| | | | | | | | | | | | We were incorrectly assuming that the coordinate's dimensionality is equal to the gradient's dimensionality. For array types, the coordinate has one more component. Fixes 12 subcases of oglconform's glsl-bif-tex-grad test. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]>
* Fix .gitignore for ralloc-testPaul Berry2012-06-041-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: Fix uninitialized members in glsl_to_tgsi_visitor constructor.Vinson Lee2012-06-021-0/+4
| | | | | | Fix uninitialized scalar field defects reported by Coverity. Signed-off-by: Vinson Lee <[email protected]>
* i965: Implement texture buffer objects on Gen6.Kenneth Graunke2012-06-022-0/+61
| | | | | | | | | | | Commit a07cf3397e332388d3599c83e50ac45511972890 added support for TBOs on Gen7, but missed Gen6. Passes piglit -t texture_buffer and oglconform's buffermapping basic.read.texture tests. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Restore depth texture state on glPopAttrib(GL_TEXTURE_BIT).Kenneth Graunke2012-06-021-0/+8
| | | | | | | | | | | | | | | | | | According to Table 6.17 in the GL 2.1 specification, DEPTH_TEXTURE_MODE, TEXTURE_COMPARE_MODE, and TEXTURE_COMPARE_FUNC need to be restored on glPopAttrib(GL_TEXTURE_BIT). Makes a number of oglconform tests happier. v2: Make restoration conditional on the ARB_shadow and ARB_depth_texture extensions, as suggested by Brian. I'm not sure that any implementations still remain that don't support those, but why not? NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* automake: Connect the libdricore target to make clean.Eric Anholt2012-06-011-0/+1
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50480 Reviewed-by: Kenneth Graunke <[email protected]>
* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-013-4/+33
| | | | | | | | | The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions.
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-012-1/+3
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* radeon/llvm: Only use indirect (vertex fetch) parameters for kernelsTom Stellard2012-06-011-2/+6
| | | | | | Kernel parameters can only be retrieved via vertex fetchs. Direct parameters (i.e parameters stored in the constant buffer) are not supported yet.
* intel: Change vendor string to "Intel Open Source Technology Center".Kenneth Graunke2012-06-011-1/+1
| | | | | | | | | | | | | | | | | | | Tungsten Graphics has not existed for several years, and the majority of ongoing development and support is done by Intel. I chose to include "Open Source Technology Center" to distinguish it from, say, the closed source Windows OpenGL driver. The one downside to this patch is that applications that pattern match against "Intel" may start applying workarounds meant for the Windows driver. However, it does seem like the right thing to do. This does change oglconform behavior. Acked-by: Eric Anholt <[email protected]> Acked-by: Ian Romanick <[email protected]> Acked-by: Eugeni Dodonov <[email protected]> Acked-by: Keith Packard <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Remove spurious printf messagesIan Romanick2012-06-011-3/+0
| | | | | | | | These look like debug messages from the switch-statement development. NOTE: This is a candidate for the 8.0 release branch. Signed-off-by: Ian Romanick <[email protected]>
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-0111-41/+124
| | | | | | Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so that the CFGStructurizer pass can run without any relying on AMDIL instructions.
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-0117-50/+50
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* radeon/llvm: Remove deadcode from the R600LowerInstructions passTom Stellard2012-06-011-46/+2
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* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-014-77/+36
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* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-016-128/+24
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