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* mesa: added OPCODE_NRM3/NRM4 instructions for vector normalization.Brian Paul2008-11-073-0/+45
| | | | | | We may emit these instructions from GLSL instead of DP3/RCP/MUL. Also, implement SSG (set sign) instruction in the interpreter.
* mesa: use _bfc0 instead of _col0 when building back face lighting.Xiang, Haihao2008-11-071-3/+2
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* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-065-18/+21
| | | | Trunc is a more accurate description; there's no type conversion involved.
* mesa: update the shader programs->TexturesUsed array at link timeBrian Paul2008-11-063-4/+26
| | | | | | | | If an application never calls glUniform() to set sampler variable values they'll remain 0 (the default value/unit). Now call _mesa_update_shader_textures_used() at link time in case glUniform() is never called. program->TextureUsed[] will then be correct for state validation.
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
| | | | | | Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
| | | | OPCODE_NOISE4 coming later.
* mesa: Fix compiler warnings on Windows.Brian Paul2008-11-051-1/+1
| | | | cherry-picked subset of a77976d2ee578d0483c64f2aa41719bbae9c1c97
* mesa: fix a GLSL array indexing codegen bugBrian Paul2008-11-052-8/+101
| | | | Expressions like array[i] + array[j] didn't work properly before.
* mesa: remove extra \n from printf stringBrian Paul2008-11-051-1/+1
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* mesa: add Initialized field to gl_uniform struct, for debugging purposes onlyBrian Paul2008-11-053-7/+16
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* mesa: fix float-valued GLSL vertex attribute variablesBrian Paul2008-11-041-8/+8
| | | | The swizzle mask for such variables wasn't set up properly.
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-029-25/+24
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* mesa: silence warningsBrian Paul2008-11-011-3/+3
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* mesa: do scope replacement for while/for loops tooBrian Paul2008-11-011-3/+7
| | | | This fixes a function inlining bug involving vars declared inside loop bodies.
* mesa: glsl tree print improvementsBrian Paul2008-11-011-1/+17
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* mesa: fix assignment / parameter passing of sampler typesBrian Paul2008-11-013-8/+29
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* mesa: additional debug flags for glsl debug/disassemblyBrian Paul2008-11-014-53/+53
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* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
* mesa: fix some bugs with precision qualifier parsingBrian Paul2008-10-319-2382/+2459
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* mesa: do scope replacement for variable initializers tooBrian Paul2008-10-311-0/+11
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* mesa: fix copy/paste error in GLSL error msgBrian Paul2008-10-311-1/+1
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* intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
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* intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
| | | | | GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage.
* intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
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* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | This is required for scatter writes in destination regions to work.
* mesa: fix a typo in the previous commitXiang, Haihao2008-10-311-1/+1
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* mesa: fix an issue in _mesa_PointParameterfv().Xiang, Haihao2008-10-301-1/+1
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* intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
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* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
* mesa: fix stand-alone glslcompiler buildBrian Paul2008-10-281-6/+2
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* intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-2817-292/+272
| | | | | | | This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
| | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
* i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
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* i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
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* intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt2008-10-271-26/+17
| | | | | | Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA.
* intel: GL_FALSE on a BO if it won't be modified when mapping this BO. ↵Xiang, Haihao2008-10-261-1/+1
| | | | (thanks Eric).
* i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao2008-10-242-4/+12
| | | | This ensures there is an unfilled batchbuffer used for emitting states again. Partial fix for #17964.
* intel: fallback for intelEmitCopyBlit.Xiang, Haihao2008-10-241-10/+39
| | | | | Use _mesa_copy_rect instead of BLT operation if dri_bufmgr_check_aperture_space still fails after flushing batchbuffer. Partial fix for #17964.
* mesa: remove calls to _mesa_adjust_image_for_convolution(), use texImage fieldsBrian Paul2008-10-231-14/+6
| | | | The texImage->Width/Height fields will have the post-convolution width/height.
* mesa: move convolution image adjustment code for glCopyTexSubImage1/2/3D()Brian Paul2008-10-221-15/+21
| | | | Do it after initial error checking, after we know the texture's internal format.
* mesa: some re-org of glCopyTexSubImage1/2/3D() error checkingBrian Paul2008-10-221-33/+32
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* mesa: in textore.c, only adjust image for convolution if image is a color formatBrian Paul2008-10-223-14/+20
| | | | | Makes things consistant with the code in teximage.c. We only want to apply convolution to color formats (not depth/index formats)
* glx: updated commentKristof Ralovich2008-10-211-1/+1
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* i915: fix carsh in i830_emit_state. (bug #17766)Xiang, Haihao2008-10-211-1/+2
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* fix span issue with really old ddx and non-tcl r100 chipsRoland Scheidegger2008-10-161-1/+1
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* mesa: fix error codes in _mesa_GetObjectParameterivARB(), bug 17861Brian Paul2008-10-161-15/+6
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