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* i965/fs: Fix regression with SIMD8 VS since b5f1a48e234d47b24df38cb562cffb894...Francisco Jerez2015-07-311-1/+2
* i965/gen9: Add hs, ds, and cs thread + urb infoBen Widawsky2015-07-301-0/+10
* i965/bxt: Use more conservative thread countsBen Widawsky2015-07-301-2/+4
* i965/skl: Add production thread counts and URB sizeBen Widawsky2015-07-301-5/+5
* vc4: Lower uniform loads to scalar in NIR.Eric Anholt2015-07-302-31/+81
* vc4: Move some FS input lowering into NIR.Eric Anholt2015-07-302-35/+50
* vc4: Move program keys to the header file.Eric Anholt2015-07-302-47/+49
* vc4: Lower NIR inputs to scalar as well.Eric Anholt2015-07-302-4/+44
* vc4: Start adding a NIR-based output lowering pass.Eric Anholt2015-07-304-7/+137
* vc4: Mark our shaders as single-threaded.Eric Anholt2015-07-302-0/+6
* vc4: Avoid leaking indirect array access UBOs.Eric Anholt2015-07-301-0/+2
* vc4: Avoid overflowing various static tables.Eric Anholt2015-07-304-4/+4
* vc4: Fix return values from recent validation changes.Eric Anholt2015-07-301-4/+4
* st/mesa: don't draw instead of asserting in transform feedbackDave Airlie2015-07-313-4/+7
* mesa: remove now unused _mesa_get_uniform_locationTimothy Arceri2015-07-302-79/+0
* mesa: remove now unused subscript validationsTimothy Arceri2015-07-302-108/+0
* mesa: fix and simplify resource query for arraysTimothy Arceri2015-07-305-92/+106
* i965/bxt: Don't use brw_device_info_skl_early on BXTNeil Roberts2015-07-301-1/+3
* glsl: set stage flag for structs and arrays in resource listTimothy Arceri2015-07-301-3/+13
* radeonsi: enable GL4.1 and update documentation (v2)Dave Airlie2015-07-301-1/+1
* radeonsi: add GS multiple streams support (v2)Dave Airlie2015-07-306-39/+127
* Delete unused functions in format parserAnuj Phogat2015-07-291-7/+0
* i965: Change the type of max_{vs, hs, ...}_threads variables to unsignedAnuj Phogat2015-07-292-7/+7
* Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()Anuj Phogat2015-07-298-26/+15
* gallium/auxiliary: Ensure c99_math.h is included.Jose Fonseca2015-07-291-1/+2
* i965/bxt: Support 3src simd16 instructionsBen Widawsky2015-07-291-3/+1
* targets/dri: scons: add missing link against libdrmEmil Velikov2015-07-291-0/+2
* svga: scons: remove unused HAVE_SYS_TYPES_H defineEmil Velikov2015-07-292-2/+0
* glsl: Avoid double promotion.Matt Turner2015-07-291-2/+2
* mesa: Avoid double promotion.Matt Turner2015-07-2914-49/+49
* mesa/math: Avoid double promotion.Matt Turner2015-07-293-46/+46
* program: Avoid double promotion.Matt Turner2015-07-291-15/+15
* swrast: Avoid double promotion.Matt Turner2015-07-2913-50/+50
* tnl: Avoid double promotion.Matt Turner2015-07-297-30/+28
* vbo: Avoid double promotion.Matt Turner2015-07-292-5/+5
* util: Avoid double promotion.Matt Turner2015-07-291-1/+1
* gallium/auxiliary: Avoid double promotion.Matt Turner2015-07-292-2/+2
* nir: Avoid double promotion.Matt Turner2015-07-291-2/+2
* i965: Use float calculations when double is unnecessary.Matt Turner2015-07-2914-34/+35
* gallium/auxiliary: Use exp2(x) instead of pow(2.0, x).Matt Turner2015-07-292-4/+4
* program: Use exp2(x) instead of pow(2.0, x).Matt Turner2015-07-291-2/+2
* mesa: Use floats for viewport bounds.Matt Turner2015-07-2914-22/+22
* glsl: Remove MSVC implementations of copysign and isnormal.Matt Turner2015-07-292-26/+2
* i965/fs: Make the default builder 64-wide before entering the optimization loop.Francisco Jerez2015-07-292-2/+7
* i965/fs: Don't set exec_all on instructions wider than the original in lower_...Francisco Jerez2015-07-291-9/+11
* i965/fs: Initialize a builder explicitly in the gen4 send dependency work-aro...Francisco Jerez2015-07-291-4/+7
* i965/cfg: Assert that cur_do/while/if pointers are non-NULL.Matt Turner2015-07-291-0/+3
* nvc0/ir: cache vertex out base so that we don't recompute againIlia Mirkin2015-07-291-8/+15
* nvc0/ir: output base for reading is based on laneidIlia Mirkin2015-07-291-0/+25
* Revert "pipe-loader: simplify pipe_loader_drm_probe"Francisco Jerez2015-07-291-4/+9
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