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* mesa: add signbit() macroBrian Paul2012-09-241-0/+7
* r600g: Set RADEON_FLUSH_KEEP_TILING_FLAGS when emitting compute csTom Stellard2012-09-241-1/+7
* Use signbit() in IS_NEGATIVE and DIFFERENT_SIGNSMatt Turner2012-09-241-19/+2
* clover: Silence narrowing conversion warnings in resource.cpp.Francisco Jerez2012-09-241-3/+3
* clover: Handle NULL value for clEnqueueNDRangeKernel local_work_sizeTom Stellard2012-09-241-7/+6
* i965/blorp: Increase Y alignment for multisampled stencil blits.Paul Berry2012-09-241-2/+7
* st/mesa: check for zero-size image in st_TestProxyTexImage()Brian Paul2012-09-241-0/+5
* mesa: Silence narrowing warnings in ff_fragment_shader's emit_texenv().Kenneth Graunke2012-09-231-4/+4
* radeon/llvm: support for interpolation intrinsicsVincent Lejeune2012-09-2210-2/+318
* draw: fix non-indexed draw calls if there's an index bufferMarek Olšák2012-09-223-8/+6
* r600g: Fix build with LLVM compilerTom Stellard2012-09-211-1/+1
* r600g: set QUANT_MODE on Cayman tooMarek Olšák2012-09-221-1/+2
* r600g: use CS helpers to emit streamout stateMarek Olšák2012-09-222-33/+14
* r600g: remove initialization of unused loop register tablesMarek Olšák2012-09-222-38/+0
* r600g: remove now-unused SURFACE_BASE_UPDATE logicMarek Olšák2012-09-223-9/+3
* r600g: remove unused CB registers from register listsMarek Olšák2012-09-222-87/+0
* r600g: atomize framebuffer stateMarek Olšák2012-09-2211-868/+664
* r600g: don't snoop context state while building shadersMarek Olšák2012-09-223-28/+43
* meta: Add on demand compilation of per target shader programsAnuj Phogat2012-09-211-57/+84
* clover: Initialize height and depth to 1 for transfersTom Stellard2012-09-211-1/+1
* pipe-loader: Remove a few debug_printfsTom Stellard2012-09-212-4/+0
* radeon/llvm: Handle loads from the constants address space.Tom Stellard2012-09-212-0/+10
* radeon/llvm: Add support for v4f32 stores on R600Tom Stellard2012-09-213-9/+27
* radeon/llvm: Add support for i8 reads on R600Tom Stellard2012-09-213-0/+25
* radeon/llvm: Expand vector fadd and fmul on R600Tom Stellard2012-09-211-0/+3
* radeon/llvm: Add optimization for FP_ROUNDTom Stellard2012-09-212-0/+27
* radeon/llvm: Replace AMDGPU pow intrinsic with the llvm versionTom Stellard2012-09-214-7/+26
* i965/blorp: Fix narrowing warnings.Paul Berry2012-09-211-3/+3
* i965: Remove brw_set_predicate_inverse(p, true) from scratch offset codeKenneth Graunke2012-09-211-1/+0
* mesa: Don't override S3TC internalFormat if data is pre-compressed.Kenneth Graunke2012-09-201-1/+1
* i965/blorp: Add support for blits between SRGB and linear formats.Kenneth Graunke2012-09-202-4/+8
* mesa: Ignore SRGB when determining compatible resolve formats.Kenneth Graunke2012-09-201-1/+2
* gallium: mention PIPE_TIMEOUT_INFINITE in the fence_finish() commentBrian Paul2012-09-201-1/+1
* llvmpipe: fix overflow bug in total texture size computationBrian Paul2012-09-201-2/+16
* r600g/llvm: rs780/rs880 are r600 asicsAlex Deucher2012-09-201-2/+2
* mesa: Allow glGetTexParameter of GL_TEXTURE_SRGB_DECODE_EXTIan Romanick2012-09-201-0/+12
* r300/compiler: Use precomputed q values in the register allocatorTom Stellard2012-09-191-1/+69
* r300g: Init regalloc state during context creationTom Stellard2012-09-198-155/+204
* r300/compiler: Don't create register classes for inputsTom Stellard2012-09-191-14/+1
* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-195-5/+18
* ra: Clarify usage of ra_set_node_reg()Tom Stellard2012-09-191-0/+2
* r600g: Invalidate texture cache when creating vertex buffers for compute v2Tom Stellard2012-09-191-1/+3
* r600g: Use LOOP_START_DX10 for loopsTom Stellard2012-09-193-2/+11
* r600g: Set the correct value of COLOR*_DIM for RATsTom Stellard2012-09-191-2/+2
* r600g: Make sure to initialize DB_DEPTH_CONTROL register for computeTom Stellard2012-09-191-1/+3
* r600g: Add some comments and debug printfs to compute codeTom Stellard2012-09-192-5/+53
* r600g: Add missing break to case statementTom Stellard2012-09-191-0/+1
* radeon/llvm: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo2012-09-1910-167/+359
* radeon/llvm: Only support 512 constant registers on R600Tom Stellard2012-09-191-1/+1
* Revert "mesa: consolidate subtexture x/y/width/height error checking code"Brian Paul2012-09-191-73/+84