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* i965: Program DWord Length in MI_FLUSH_DWAnuj Phogat2017-11-142-2/+2
* anv/gen10: Enable float blend optimizationAnuj Phogat2017-11-141-0/+12
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
* anv/gen10: Implement WaSampleOffsetIZ workaroundAnuj Phogat2017-11-141-0/+61
* mesa/st: add missing copyright headers to memoryobjects filesAndres Rodriguez2017-11-142-0/+48
* mesa: minor tidy up for memory object error stringsAndres Rodriguez2017-11-141-16/+14
* broadcom/vc4: fix indentation in vc4_screen.cAndres Rodriguez2017-11-141-8/+8
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-141-13/+3
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-141-2/+23
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-141-4/+4
* swr/rast: Faster emulated simd16 permuteTim Rowley2017-11-141-23/+11
* swr/rast: Use gather instruction for i32gather_ps on simd16/avx512Tim Rowley2017-11-141-11/+1
* egl/wayland: Add a fallback when fourcc query isn't supportedDerek Foreman2017-11-141-2/+30
* radeonsi: remove has_cp_dma, has_streamout flags (v2)Marek Olšák2017-11-143-20/+2
* i965: implement (un)mapImageJulien Isorce2017-11-141-2/+63
* radv: force enable LLVM sisched for The Talos PrincipleSamuel Pitoiset2017-11-141-0/+20
* radv: add nosisched debug optionSamuel Pitoiset2017-11-142-0/+10
* spirv: fix typo on DO NOT EDIT headerAlejandro Piñeiro2017-11-141-1/+1
* radv: Free temporary syncobj after waiting on it.Bas Nieuwenhuizen2017-11-141-4/+18
* radv: Free syncobj with multiple imports.Bas Nieuwenhuizen2017-11-141-2/+8
* i965: Track the depth and render caches separatelyJason Ekstrand2017-11-135-22/+26
* i965/blorp: Add more destination flushingJason Ekstrand2017-11-131-1/+6
* i965: Add more precise cache tracking helpersJason Ekstrand2017-11-136-13/+49
* i965: Add stencil buffers to cache set regardless of stencil texturingJason Ekstrand2017-11-131-3/+1
* i965: Switch over to fully external-or-not MOCS schemeJason Ekstrand2017-11-133-29/+11
* i965: Use PTE MOCS for all external buffersJason Ekstrand2017-11-132-10/+18
* intel/blorp: Make the MOCS setting part of blorp_addressJason Ekstrand2017-11-136-33/+44
* anv/blorp: Add a device parameter to blorp_surf_for_anv_imageJason Ekstrand2017-11-131-22/+34
* intel/blorp: Use mocs.tex for depth stencilJason Ekstrand2017-11-131-5/+1
* intel/tools/error: Decode compute shaders.Kenneth Graunke2017-11-131-7/+42
* intel/tools/error: Use do-while for field iterator loops.Kenneth Graunke2017-11-131-6/+6
* intel/tools/error: Decode shaders while decoding batch commands.Kenneth Graunke2017-11-131-85/+49
* intel/tools/error: Save error state sections and decode them later.Kenneth Graunke2017-11-131-37/+58
* intel/tools/error: Fix null termination of ring name string.Kenneth Graunke2017-11-131-0/+1
* intel/tools/error: Drop unused MAX_RINGS #define.Kenneth Graunke2017-11-131-2/+0
* intel/tools/error: Refactor buffer matching, add more buffers.Kenneth Graunke2017-11-131-62/+30
* intel/tools/error: Only decode a few sections of error states.Kenneth Graunke2017-11-131-1/+3
* intel/tools/error: Drop unused parameters from decode() helper.Kenneth Graunke2017-11-131-5/+3
* intel/tools/error: Drop support for non-ascii85 encoded error states.Kenneth Graunke2017-11-131-35/+4
* intel/tools/error: Do ascii85 decode first.Kenneth Graunke2017-11-131-31/+29
* egl/haiku: Correct invalid void* conversion in callocAlexander von Gluck IV2017-11-131-1/+2
* meson: Remove build_by_default from amd codeDylan Baker2017-11-133-3/+3
* meson: Don't build intel shared components by defaultDylan Baker2017-11-134-6/+3
* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-1313-34/+25
* r600/shader: handle bitfield extract semantics properly.Dave Airlie2017-11-141-4/+53
* r600: handle bitfieldInsert corner case.Dave Airlie2017-11-141-1/+39
* r600: add gs tri strip adjacency fix.Dave Airlie2017-11-144-5/+62
* r600: fix isoline tess factor component swapping.Dave Airlie2017-11-141-0/+7
* r600/shader: reserve first register of vertex shader.Dave Airlie2017-11-141-2/+4
* r600: don't emit atomic save if we have no atomic counters.Dave Airlie2017-11-141-0/+3
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