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* gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERSIlia Mirkin2016-10-2218-1/+20
| | | | | | | | | | | | | | This allows the driver to signal that it can't handle random interleaving of attributes across buffers. This is required for ARB_transform_feedback3, and it's initialized to whatever the previous value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for nv50 where it is disabled. Note that the proprietary drivers never expose ARB_transform_feedback3 on any GT21x's (where nouveau previously did), and after some effort I was unable to get it to work. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0/ir: remove outdated comment about SHLADDSamuel Pitoiset2016-10-222-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Avoid making temporaries for assignments to NIR registers.Eric Anholt2016-10-211-35/+79
| | | | | | | | | | | | | | | | | | | | | | | Getting stores to NIR regs to not generate new MOVs is tricky, since the result we're trying to store into the NIR reg may have been from a conditional update of a temp, or a series of packed writes. The easiest solution seems to be to require that nir_store_dest()'s arg comes from an SSA temp. This causes us to put in a few more temporary MOVs in the NIR SSA dest case, but copy propagation successfully cleans those up. The shader-db change is modest: total instructions in shared programs: 93774 -> 93598 (-0.19%) instructions in affected programs: 14760 -> 14584 (-1.19%) total estimated cycles in shared programs: 212135 -> 211946 (-0.09%) estimated cycles in affected programs: 27005 -> 26816 (-0.70%) but I was seeing patterns in some register-allocation failures in DEQP tests that looked like the extra MOVs would increase maximum register pressure in loops. Some debug code indicates that that's not the case, though I'm still a bit confused by that result.
* vc4: Add a comment with discussion of how simulation works.Eric Anholt2016-10-211-0/+25
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* vc4: Move simulator winsys mapping and tracking to the simulator.Eric Anholt2016-10-213-20/+56
| | | | | One tiny hack is left in vc4_bufmgr.c for what kind of mapping we got so that we can free it.
* vc4: Move simulator memory management to a u_mm.h heap.Eric Anholt2016-10-215-41/+208
| | | | | | Now we aren't limited to 256MB total allocated across a driver instance, just 256MB at one time. We're still copying in and out, which should get fixed.
* vc4: Move simulator globals into a struct.Eric Anholt2016-10-212-34/+29
| | | | | I would like to put a couple more things in here, so it's time to package it up.
* vc4: Restructure the simulator mode.Eric Anholt2016-10-215-84/+182
| | | | | | | | | | | | | Rather than having simulator mode changes scattered around vc4_bufmgr.c and vc4_screen.c, make vc4_bufmgr.c just call a vc4_simulator_ioctl, which then dispatches to a corresponding implementation. This will give the simulator support a centralized place to do tricks like storing most BOs directly in simulator memory rather than copying in and out. This leaves special casing of mmaping BOs and execution, because of the winsys mapping.
* vc4: Fix termination of the initial scan for branch targets.Eric Anholt2016-10-211-11/+8
| | | | | | | | | | | | | The loop is scanning until the original max_ip (size of the BO), but we want to not examine any code after the PROG_END's delay slots. There was a block trying to do that, except that we had some early continue statements if the signal wasn't a PROG_END or a BRANCH. The failure mode would be that a valid shader is rejected because some undefined memory after the PROG_END slots is parsed as a branch and the rest of its setup is illegal. I haven't seen this in the wild, but valgrind was complaining and the new userland simulator code started triggering it.
* anv: Always use the full driver path in the intel_icd.*.jsonJason Ekstrand2016-10-212-8/+2
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: "13.0" <[email protected]>
* anv: Suffix the intel_icd file with the host CPUJason Ekstrand2016-10-212-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vulkan has a multi-arch problem... The idea behind the Vulkan loader is that you have a little json file on your disk that tells the loader where to find drivers. The loader looks for these json files in standard locations, and then goes and loads the my_driver.so's that they specify. This allows you as a driver implementer to put their driver wherever on the disk they want so long as the ICD points in the right place. For a multi-arch system, however, you may have multiple libvulkan_intel.so files installed that the loader needs to pick depending on architecture. Since the ICD file format does not specify any architecture information, you can't tell the loader where to find the 32-bit version vs. the 64-bit version. The way that packagers have been dealing with this is to place libvulkan_intel.so in the top level lib directory and provide just a name (and no path) to the loader. It will then use the regular system search paths and find the correct driver. While this solution works fine for distro-installed Vulkan drivers, it doesn't work so well for user-installed drivers because they may put it in /opt or $HOME/.local or some other more exotic location. In this case, you can't use an ICD json file with just a library name because it doesn't know where to find it; you also have to add that to your library lookup path via LD_LIBRARY_PATH or similar. This patch handles both use-cases by taking advantage of the fact that the loader dlopen()s each of the drivers and, if one dlopen() calls fails, it silently continues on to open other drivers. By suffixing the icd file, we can provide two different json files: intel_icd.x86_64.json and intel_icd.i686.json with different paths. Since dlopen() will only succeed on the libvulkan_intel.so of the right arch, the loader will happily ignore the others and load that one. This allows us to properly handle multi-arch while still providing a full path so user installs will work fine. I tested this on my Fedora 25 machine with 32 and 64-bit builds of our Vulkan driver installed and 32 and 64-bit builds of crucible. It seems to work just fine. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: "13.0" <[email protected]>
* radeonsi: fix a regression in si_eliminate_const_outputNicolai Hähnle2016-10-211-4/+3
| | | | | | | | | | A constant value of float type is not necessarily a ConstantFP: it could also be a constant expression that for some reason hasn't been folded. This fixes a regression in GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 that was introduced by commit 3ec9975555d1cc5365413ad9062f412904f944a3. Reviewed-by: Marek Olšák <[email protected]>
* nv50,nvc0: don't keep track of whether fb rt0 is integer-onlyIlia Mirkin2016-10-216-44/+22
| | | | | | | | | | This reverts commits 1af0641db345209c076e9b1ba4dca7524541671a and a6ad49cbbd599aec054d0a3163fff5ad724f2b18. st/mesa adjusts the rasterizer state for us now. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* Revert "Revert "mapi: export all GLES 3.2 functions in libGLESv2.so""Francisco Jerez2016-10-201-0/+12
| | | | | | | | | This reverts commit 85e9bbc14d93fa7166c9ae075ee7ae29a8313e3f. The previous commit should help with the scons build failure caused by the original commit. Cc: [email protected] Reviewed-by: Dylan Baker <[email protected]>
* glapi: Move PrimitiveBoundingBox and BlendBarrier definitions into ES3.2 ↵Francisco Jerez2016-10-201-13/+17
| | | | | | | | | | | | | | | | | category. These two GLES 3.2 entry points were being defined in the category of the ARB_ES3_2_compatibility and KHR_blend_equation_advanced extensions respectively instead of in the ES3.2 category. Defining them in the ES3.2 category makes sure that the gl_procs.py generator emits declarations in the glprocs.h header file for the unsuffixed GLES-only entry points that PrimitiveBoundingBoxARB and BlendBarrierKHR respectively alias. This should avoid a compilation failure during scons builds in combination with "mapi: export all GLES 3.2 functions in libGLESv2.so". Cc: [email protected] Reviewed-by: Dylan Baker <[email protected]>
* util: Include string.h in bitscan.h.Vinson Lee2016-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix build error with clang. Compiling src/compiler/glsl/link_varyings.cpp ... In file included from src/compiler/glsl/link_varyings.cpp:33: In file included from src/compiler/glsl/glsl_symbol_table.h:34: In file included from src/compiler/glsl/ir.h:33: In file included from src/compiler/glsl_types.h:29: /usr/include/string.h:518:12: error: exception specification in declaration does not match previous declaration extern int ffs (int __i) __THROW __attribute__ ((__const__)); ^ src/util/bitscan.h:51:13: note: expanded from macro 'ffs' ^ src/util/bitscan.h:96:18: note: previous declaration is here const int i = ffs(*mask) - 1; ^ src/util/bitscan.h:51:13: note: expanded from macro 'ffs' ^ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97952 Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* nvc0: do not break 3D state by pushing MS coordinates on FermiSamuel Pitoiset2016-10-201-43/+44
| | | | | | | | | | | | | | | | | | Long story short, 3D and CP are aliased on Fermi and initializing compute after pushing the MS sample coordinate offsets seems to corrupt 3D state for weird reasons. I still don't have the faintest clue what is going on, but this seems to only affect Fermi generation. A possible fix could be to use two different channels, one for 3D and one for CP. This fixes a bunch of regressions pinpointed by piglit. Fixes: "nvc0: fix up image support for allowing multiple samples" Cc: "13.0" <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: translate compute shaders at program creationSamuel Pitoiset2016-10-201-0/+4
| | | | | | | This makes shader-db reports results for compute shaders. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vbo: clean up with 'indent', whitespace fixes, etc in vbo_exec_array.cBrian Paul2016-10-201-252/+276
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* vbo: whitespace fixes and reformatting in vbo_exec_api.cBrian Paul2016-10-201-42/+64
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* vbo: minor clean-up in vbo_exec_api.cBrian Paul2016-10-201-5/+2
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* vbo: move attribute type assignmentBrian Paul2016-10-201-1/+2
| | | | | | | | | | If the attribute type is changing, we would have found that earlier in the ATTR_UNION() macro and would have called vbo_exec_fixup_vertex(). So move the assignment into that function so we don't do it every time. No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* vbo: rename reset_attrfv() to vbo_reset_all_attr()Brian Paul2016-10-201-4/+6
| | | | | | Use a better name. Reviewed-by: Charmaine Lee <[email protected]>
* vbo: make vbo_reset_attr() staticBrian Paul2016-10-202-3/+5
| | | | | | Not called from any other file. Reviewed-by: Charmaine Lee <[email protected]>
* vbo: trivial indentation fix in vbo_exec_api.cBrian Paul2016-10-201-1/+1
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* gallivm: try to fix build with LLVM <= 3.4 due to missing CallSite.hMarek Olšák2016-10-201-1/+5
| | | | | Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* radeonsi: fix build of si_eliminate_const_vs_outputs on LLVM <= 3.8Marek Olšák2016-10-201-3/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: add wrappers for missing functions in LLVM <= 3.8Marek Olšák2016-10-202-0/+27
| | | | | | radeonsi needs these. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix 64-bit loads from LDSNicolai Hähnle2016-10-201-1/+1
| | | | | | | | | Fixes spec/arb_tessellation_shader/execution/dvec[23]-vs-tcs-tes, among others. Cc: "12.0 13.0" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: only set primitive_restart when the restart index is in rangeNicolai Hähnle2016-10-201-2/+13
| | | | | | | | | | | | | Even when enabled, primitive restart has no effect when the restart index is larger than the representable values in the index buffer. Fixes GL45-CTS.gtf31.GL3Tests.primitive_restart.primitive_restart_upconvert for radeonsi VI. v2: add an explanatory comment Cc: "12.0 13.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1)
* st/glsl_to_tgsi: sort input and output decls by TGSI indexNicolai Hähnle2016-10-201-0/+28
| | | | | | | | Fixes a regression introduced by commit 777dcf81b. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98307 Reviewed-by: Marek Olšák <[email protected]> Cc: 13.0 <[email protected]>
* st/glsl_to_tgsi: fix block copies of arrays of structsNicolai Hähnle2016-10-201-2/+4
| | | | | | | | | | Use a full writemask in this case. This is relevant e.g. when a function has an inout argument which is an array of structs. v2: use C-style comment (Timothy Arceri) Reviewed-by: Marek Olšák <[email protected]> (v1) Cc: 13.0 <[email protected]>
* st/glsl_to_tgsi: fix block copies of arrays of doublesNicolai Hähnle2016-10-201-0/+1
| | | | | | | | | Set the type of the left-hand side to the same as the right-hand side, so that when the base type is double, the writemask of the MOV instruction is properly fixed up. Reviewed-by: Marek Olšák <[email protected]> Cc: 13.0 <[email protected]>
* glsl: Indirect array indexing on non-last SSBO member must fail compilationIago Toral Quiroga2016-10-202-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the changes in comit 5b2675093e863a52, we moved this check to the linker, but the spec expects this to be checked at compile-time. There are dEQP tests that expect an error at compile time and the spec seems to confirm that expectation: "Except for the last declared member of a shader storage block (section 4.3.9 “Interface Blocks”), the size of an array must be declared (explicitly sized) before it is indexed with anything other than an integral constant expression. The size of any array must be declared before passing it as an argument to a function. Violation of any of these rules result in compile-time errors. It is legal to declare an array without a size (unsized) and then later redeclare the same name as an array of the same type and specify a size, or index it only with integral constant expressions (implicitly sized)." Commit 5b2675093e863a52 tries to take care of the case where we have implicitly sized arrays in SSBOs and it does so by checking the max_array_access field in ir_variable during linking. In this patch we change the approach: we look for indirect access on SSBO arrays, and when we find one, we emit a compile-time error if the accessed member is not the last in the SSBO definition. There is a corner case that the specs do not address directly though and that dEQP checks for: the case of an unsized array in an SSBO definition that is not defined last but is never used in the shader code either. The following dEQP tests expect a compile-time error in this scenario: dEQP-GLES31.functional.debug.negative_coverage.callbacks.shader.compile_compute_shader dEQP-GLES31.functional.debug.negative_coverage.get_error.shader.compile_compute_shader dEQP-GLES31.functional.debug.negative_coverage.log.shader.compile_compute_shader However, since the unsized array is never used it is never indexed with a non-constant expression, so by the spec quotation above, it should be valid and the tests are probably incorrect. Reviewed-by: Nicolai Hähnle <[email protected]>
* nv50/ir: process texture offset sources as regular sourcesIlia Mirkin2016-10-191-53/+94
| | | | | | | | | | | | | | | With ARB_gpu_shader5, texture offsets can be any source, including TEMPs and IN's. Make sure to process them as regular sources so that we pick up masks, etc. This should fix some CTS tests that feed offsets directly to textureGatherOffset, and we were not picking up the input use, thus not advertising it in the shader header. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dave Airlie <[email protected]> Cc: 12.0 13.0 <[email protected]>
* nv50,nvc0: avoid reading out of bounds when getting bogus so infoIlia Mirkin2016-10-192-2/+8
| | | | | | | | | The state tracker tries to attach the info to the wrong shader. This is easy enough to protect against. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: 12.0 13.0 <[email protected]>
* wsi/wayland: fix error pathEric Engestrom2016-10-201-0/+4
| | | | | | | Fixes: 1720bbd353d87412754f ("anv/wsi: split image alloc/free out to separate fns.") Cc: "13.0" <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* anv: drop unused zero macro.Dave Airlie2016-10-201-2/+0
| | | | | | | I can't see this being used anywhere. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use emit_icmp for samples_identicalDave Airlie2016-10-201-1/+1
| | | | | | | | | On a debug llvm build we'd assert on the next compare when the return from samples_identical was i1 instead of i32. Cc: "13.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/cs: Don't use a thread channel ID for small local sizesJordan Justen2016-10-191-2/+11
| | | | | | | | | | | | | | | | | When the local group size is 8 or less, we will execute the program at most 1 time. Therefore, the local channel ID will always be 0. By using a constant 0 in this case we can prevent using push constant data. This is not expected to be common a occurance in real applications, but it has been seen in tests. We could extend this optimization to 16 and 32 for SIMD16 and SIMD32, but it gets a bit more complicated, because this optimization is currently being done early on, before we have decided the SIMD size. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/cs: Use udiv/umod for local IDsJordan Justen2016-10-191-1/+1
| | | | | | | This allows for more optimizations relating to power-of-two divisions. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove unused LocalSizeVariableTimothy Arceri2016-10-202-6/+0
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0/ir: simplify predicate logic for GK104 atomic operationsSamuel Pitoiset2016-10-191-14/+7
| | | | | | | | The predicate is always CC_NOT_P as defined in processSurfaceCoordsNVE4(), so we only want to emit OR. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: remove useless NVC0LoweringPass::gMemBaseSamuel Pitoiset2016-10-191-4/+1
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nv50/ir: print CCTL subops in debug modeSamuel Pitoiset2016-10-191-0/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nir: Optimize integer division and modulus with 1Ian Romanick2016-10-191-0/+4
| | | | | | | | | | | | | | The previous power-of-two rules didn't catch idiv (because i965 doesn't set lower_idiv) and imod cases. The udiv and umod cases should have been caught, but I included them for orthogonality. This fixes silly code observed from compute shaders with local_size_[xy] = 1. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98299 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: eliminate trivial constant VS outputsMarek Olšák2016-10-193-2/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These constant value VS PARAM exports: - 0,0,0,0 - 0,0,0,1 - 1,1,1,0 - 1,1,1,1 can be loaded into PS inputs using the DEFAULT_VAL field, and the VS exports can be removed from the IR to save export & parameter memory. After LLVM optimizations, analyze the IR to see which exports are equal to the ones listed above (or undef) and remove them if they are. Targeted use cases: - All DX9 eON ports always clear 10 VS outputs to 0.0 even if most of them are unused by PS (such as Witcher 2 below). - VS output arrays with unused elements that the GLSL compiler can't eliminate (such as Batman below). The shader-db deltas are quite interesting: (not from upstream si-report.py, it won't be upstreamed) PERCENTAGE DELTAS Shaders PARAM exports (affected only) batman_arkham_origins 589 -67.17 % bioshock-infinite 1769 -0.47 % dirt-showdown 548 -2.68 % dota2 1747 -3.36 % f1-2015 776 -4.94 % left_4_dead_2 1762 -0.07 % metro_2033_redux 2670 -0.43 % portal 474 -0.22 % talos_principle 324 -3.63 % warsow 176 -2.20 % witcher2 1040 -73.78 % ---------------------------------------- All affected 991 -65.37 % ... 9681 -> 3353 ---------------------------------------- Total 26725 -10.82 % ... 58490 -> 52162 v2: treat Undef as both 0 and 1 Reviewed-by: Nicolai Hähnle <[email protected]> (v1) Tested-by: Edmondo Tommasina <[email protected]> (v1)
* nv50/ir: silent TGSI_PROPERTY_FS_DEPTH_LAYOUTSamuel Pitoiset2016-10-191-0/+1
| | | | | | | | Found that information message while replaying a trace from Metro 2033 Redux. Mark that property as useless for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: remove cb0_is_integer handlingMarek Olšák2016-10-193-13/+3
| | | | | | st/mesa does this for us. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: disable alpha-test, alpha-to-coverage, alpha-to-one for integer FBsMarek Olšák2016-10-192-2/+4
| | | | | | v2: rebased Reviewed-by: Brian Paul <[email protected]>
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