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* virgl: fix reference counting of prime handlesRob Herring2016-02-022-12/+33
| | | | | | | | | | The virgl reference counting of buffers is broken for prime fd buffers. Each prime fd passed into virgl_drm_winsys_resource_create_handle creates a new resource. The solution requires creating a separate hash table to track flink names separately from prime handles. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: reuse screen when fd is already openRob Herring2016-02-025-8/+97
| | | | | | | | | | It is necessary to share the screen between mesa and gralloc to properly ref count resources. This implements a hash lookup on the file description to re-use an already created screen. This is a similar implementation as freedreno and radeon. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nouveau/video: wrap assertion within #ifndef NDEBUGMauro Rossi2016-02-011-0/+2
| | | | | | | | | | | | The change is necessary to avoid the following building error in android: external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next': external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function) assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]); ^ This matches the declaration of the variables in question. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: treat a write as a read for range purposesIlia Mirkin2016-02-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use this logic to detect live ranges and then do plain renaming across the whole codebase. As such, to prevent WaW hazards, we have to treat a write as if it were also a read. For example, the following sequence was observed before this patch: 13: UIF TEMP[6].xxxx :0 14: ADD TEMP[6].x, CONST[6].xxxx, -IN[3].yyyy 15: RCP TEMP[7].x, TEMP[3].xxxx 16: MUL TEMP[3].x, TEMP[6].xxxx, TEMP[7].xxxx 17: ADD TEMP[6].x, CONST[7].xxxx, -IN[3].yyyy 18: RCP TEMP[7].x, TEMP[3].xxxx 19: MUL TEMP[4].x, TEMP[6].xxxx, TEMP[7].xxxx While after this patch it becomes: 13: UIF TEMP[7].xxxx :0 14: ADD TEMP[7].x, CONST[6].xxxx, -IN[3].yyyy 15: RCP TEMP[8].x, TEMP[3].xxxx 16: MUL TEMP[4].x, TEMP[7].xxxx, TEMP[8].xxxx 17: ADD TEMP[7].x, CONST[7].xxxx, -IN[3].yyyy 18: RCP TEMP[8].x, TEMP[3].xxxx 19: MUL TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx Most importantly note that in the first example, the second RCP is done on the result of the MUL while in the second, the second RCP should have the same value as the first. Looking at the GLSL source, it is apparent that both of the RCP's should have had the same source. Looking at what's going on, the GLSL looks something like float tmin_8; float tmin_10; tmin_10 = tmin_8; ... lots of code ... tmin_8 = tmpvar_17; ... more code that never looks at tmin_8 ... And so we end up with a last_read somewhere at the beginning, and a first_write somewhere at the bottom. For some reason DCE doesn't remove it, but even if that were fixed, DCE doesn't handle 100% of cases, esp including loops. With the last_read somewhere high up, we overwrite the previously correct (and large) last_read with a low one, and then proceed to decide to merge all kinds of junk onto this temp. Even if that weren't the case, and there were just some writes after the last read, then we might still overwrite a merged value with one of those. As a result, we should treat a write as a last_read for the purpose of determining the live range. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Cc: [email protected]
* i965/gen7+: Use NIR for lowering of pack/unpack opcodes.Matt Turner2016-02-013-19/+29
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Implement nir_op_pack_uvec2_to_uint.Matt Turner2016-02-011-0/+18
| | | | | | | And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced by lowering pack[SU]norm4x8 which the vec4 backend does not need. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering support for unpacking opcodes.Matt Turner2016-02-012-0/+32
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering support for packing opcodes.Matt Turner2016-02-014-0/+66
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Implement support for extract_word.Matt Turner2016-02-015-0/+56
| | | | | | The vec4 backend will lower it. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add opcodes to extract bytes or words.Matt Turner2016-02-013-0/+28
| | | | | | The uint versions zero extend while the int versions sign extend. Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl: Remove 2x16 half-precision pack/unpack opcodes.Matt Turner2016-02-019-170/+8
| | | | | | i965/fs was the only consumer, and we're now doing the lowering in NIR. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.Matt Turner2016-02-013-11/+7
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add lowering of nir_op_unpack_half_2x16.Matt Turner2016-02-012-4/+29
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Make separate nir_options for scalar/vector stages.Matt Turner2016-02-011-28/+33
| | | | | | | We'll want to have different lowering options set for scalar/vector stages. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Move brw_compiler_create() to new brw_compiler.c.Matt Turner2016-02-015-133/+161
| | | | | | | A future patch will want to use designated initalizers, which aren't available in C++, but this is C. Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Make argument order of unop_convert match binop_convert.Matt Turner2016-02-011-10/+10
| | | | | | Strangely the return and parameter types were reversed. Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: enable enums for OES_geometry_shaderMarta Lofstedt2016-02-012-36/+98
| | | | | | | | | | | | | Enable GL_OES_geometry_shader enums for OpenGL ES 3.1. V4: EXTRA tokens updated according to comments from Ilia Mirkin. V5: Account for check_extra does not evaluate "or" lazy. Fix issues with EXTRA_EXT_FB_NO_ATTACH_CS. Signed-off-by: Marta Lofstedt <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: Add DragonFly supportFrançois Tigeot2016-01-311-1/+1
| | | | | Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* nv50/ir: get rid of memory stores with nop valuesIlia Mirkin2016-01-301-0/+6
| | | | | | | | | | | | | | | | | | | | This happens especially with exports and varying packing, where the last bits aren't always filled in. We end up trying to do quad-wide stores, which ends up being a lot of register moves that carefully preserve the nop value. Instead don't do the stores. total instructions in shared programs : 6131375 -> 6125267 (-0.10%) total gprs used in shared programs : 910139 -> 895501 (-1.61%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst helped 0 7442 4693 hurt 0 90 2687 Most of the helped/hurt instruction changes are by one or two ops because can no longer do quad-wide stores in all cases. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix false global CSE on instructions with multiple defsIlia Mirkin2016-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | If an instruction has multiple defs, we have to do a lot more checks to make sure that we can move it forward. Among other things, various code likes to do a, b = tex() if () c = a else c = b which means that a single phi node will have results pointing at the same instruction. We obviously can't propagate the tex in this case, but properly accounting for this situation is tricky. Just don't try for instructions with multiple defs. This fixes about 20 shaders in shader-db, including the dolphin efb2ram shader. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nv50,nvc0: fix buffer clearing to respect engine alignment requirementsIlia Mirkin2016-01-302-52/+247
| | | | | | | | | | | | | | | It appears that the nvidia render engine is quite picky when it comes to linear surfaces. It doesn't like non-256-byte aligned offsets, and apparently doesn't even do non-256-byte strides. This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0. As a side-effect this also allows RGB32 clears to work via GPU data upload instead of synchronizing the buffer to the CPU (nvc0 only). Signed-off-by: Ilia Mirkin <[email protected]> # tested on GF108, GT215 Tested-by: Nick Sarnie <[email protected]> # GK208 Cc: [email protected]
* freedreno/ir3: ignore clip-vertex varyingRob Clark2016-01-301-1/+4
| | | | | | | | | | | Since we emulate clip-planes, the clip-vertex is used within the VS itself (thanks to nir_lower_clip). So just ignore it as a VS output. Fixes a boatload of piglit tests that were asserting on unknown varying slot. (Also unrelated spelling/typo fix.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't ignore local varsRob Clark2016-01-301-1/+7
| | | | | | | | | | | With glsl_to_nir we end up with local variables, instead of global, for arrays. Note that we'll eventually have to do something more clever, I think, when we support multiple functions, but that will probably take some work in a few places. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle tex instrs w/ const offsetRob Clark2016-01-301-0/+16
| | | | | | Something we start to see with glsl_to_nir. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: support load_front_face intrinsicRob Clark2016-01-301-2/+14
| | | | | | | With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE. But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic. Signed-off-by: Rob Clark <[email protected]>
* freedreno: limit string marker to max packet sizeRob Clark2016-01-301-0/+3
| | | | | | Experimentally derived max size. Signed-off-by: Rob Clark <[email protected]>
* nvc0: avoid crashing when there are holes in vertex array bindingsIlia Mirkin2016-01-291-3/+13
| | | | | | | | | When using the "shared" vertex array configuration strategy, we bind each of the buffers as a separate array. However there can be holes in such vertex buffer lists, so just emit a disable for those. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* nvc0: enable atomic counters and ssboIlia Mirkin2016-01-292-2/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: handle new TGSI MEMBAR opcodeIlia Mirkin2016-01-291-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin2016-01-293-5/+8
| | | | | | | Teach the emitter that the two registers are sequential, and drop the second arg entirely, in favor of a double-wide first argument. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for indirect buffer loadingIlia Mirkin2016-01-292-10/+31
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add SUQ op by reading the info from driver constbufIlia Mirkin2016-01-296-3/+21
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-296-11/+147
| | | | | | | This largely leaves the existing image logic alone. When image support is added this will have to be harmonized somehow. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: handle shader buffer memory barrierIlia Mirkin2016-01-291-0/+4
| | | | | | | Issue a MEM_BARRIER. No idea if this is sufficient. As there are no tests for this, it'll have to do for now. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add state management for shader buffersIlia Mirkin2016-01-295-8/+111
| | | | | | | (address, length) pairs are uploaded to the driver constbuf as well to make these values available to the shaders. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: double per-shader stage driver constants areaIlia Mirkin2016-01-293-15/+15
| | | | | | We need to store a lot more info now with per-buffer address/size. Signed-off-by: Ilia Mirkin <[email protected]>
* trace: add support for set_shader_buffersIlia Mirkin2016-01-293-0/+60
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add arg_begin/arg_end around buffer array Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: enable ARB_shader_storage_buffer_object when supportedIlia Mirkin2016-01-291-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add shader buffer barrier bitIlia Mirkin2016-01-292-0/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add support for memory barrier intrinsicsIlia Mirkin2016-01-291-0/+45
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v2) v1 -> v2: use TGSI_MEMBAR defines
* st/mesa: use RESQ to find buffer sizeIlia Mirkin2016-01-291-4/+18
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: add support for SSBO binding and GLSL intrinsicsIlia Mirkin2016-01-299-8/+397
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> v1 -> v2: some 80 char reformatting
* st/mesa: add atomic counter supportIlia Mirkin2016-01-2910-8/+330
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add PROGRAM_IMMEDIATE, PROGRAM_BUFFERIlia Mirkin2016-01-292-1/+2
| | | | | | | | | This makes PROGRAM_IMMEDIATE a first-class gl_register_file type, and adds PROGRAM_BUFFER to the list. These are used purely inside glsl_to_tgsi conversion. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: keep track of ssbo variable being accessed, add access paramsIlia Mirkin2016-01-295-6/+57
| | | | | | | | | | | | | | | | | | | | Currently any access params (coherent/volatile/restrict) are being lost when lowering to the ssbo load/store intrinsics. Keep track of the variable being used, and bake its access params in as the last arg of the load/store intrinsics. If the variable is accessed via an instance block, then 'variable' points to the instance block variable and not the field inside the instance block that we are accessing. In order to check access parameters for the field itself we need to detect this case and keep track of the corresponding field struct so we can extract the specific field access information from there instead. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add tracking of struct field v2 -> v3: minor adjustments based on Iago's feedback Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl: always initialize image_* fields, copy them on interface initIlia Mirkin2016-01-293-1/+12
| | | | | | | | | Interfaces can have image properties set in case they are buffer interfaces. Make sure not to lose this information. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsicsIlia Mirkin2016-01-293-2/+24
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (v1) v1 -> v2: add defines for the various bits Reviewed-by: Roland Scheidegger <[email protected]>
* winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*Michel Dänzer2016-01-291-10/+9
| | | | | | | | | | | In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created in VRAM if they get evicted to GTT. In general there's no need to restrict any of the flags to any particular domains. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESSMichel Dänzer2016-01-291-0/+2
| | | | | | | | | | | | | | | | Failing to do this was resulting in the kernel driver unnecessarily leaving open the possibility of CPU access to tiled BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862 (This change shouldn't be backported to stable branches, because released versions of xf86-video-amdgpu unnecessarily try to map the front buffer) Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* nv50/ir: optimize mad/fma with third argument 0 to mulKarol Herbst2016-01-281-0/+21
| | | | | | | | | | | | | | | Very modest effect, but it's clearly the right thing to do. total instructions in shared programs : 6131491 -> 6131398 (-0.00%) total gprs used in shared programs : 910157 -> 910131 (-0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) local gpr inst bytes helped 0 55 85 85 hurt 0 26 20 20 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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