aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* aco: compact various Instruction classesDaniel Schürmann2020-01-107-100/+99
| | | | | | | No pipelinedb changes. Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3332>
* mesa/st: fix a memory leak in get_versionAndrii Simiklit2020-01-101-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch prevents memory leak in get_version function in st_manager.c This issue was found by valgrind: 16 bytes in 1 blocks are definitely lost in loss record 6 of 1,418 at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so) by 0x63D9476: st_init_extensions (st_extensions.c:1679) by 0x63B803B: get_version (st_manager.c:1271) by 0x63B8124: st_api_query_versions (st_manager.c:1289) by 0x63266EF: dri_init_screen_helper (dri_screen.c:583) by 0x6321B12: dri2_init_screen (dri2.c:2110) by 0x631AACC: driCreateNewScreen2 (dri_util.c:155) by 0x5D58192: dri3_create_screen (dri3_glx.c:897) by 0x5D39829: AllocAndFetchScreenConfigs (glxext.c:815) by 0x5D39C57: __glXInitialize (glxext.c:941) by 0x5D3290A: GetGLXPrivScreenConfig (glxcmds.c:174) by 0x5D34F38: glXQueryExtensionsString (glxcmds.c:1307) Fixes: eca8032f20d0970184843d98e2bddb688e94a3a9 ("gallium: Add ARB_gl_spirv support") Reviewed-by: Gert Wollny <[email protected]> Signed-off-by: Andrii Simiklit <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3345>
* freedreno/drm: Fix memory leak in softpin implementationLasse Lopperi2020-01-101-0/+2
| | | | | | | | | | | | | | | | Free the memory allocated for cmds/reloc_bos array when destoying the associated ringbuffer. For similar fix for the non-softpin implementation see: https://gitlab.freedesktop.org/mesa/mesa/commit/d014af98b7afc69f4f733c8b8b6f2e3438e68407 Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2324 Fixes: f3cc0d2 ("freedreno: import libdrm_freedreno + redesign submit") Signed-off-by: Lasse Lopperi <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3342>
* aco: limit register usage for large work groupsRhys Perry2020-01-104-7/+33
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* ac/llvm: Fix ac_build_reduce in wave32 mode.Timur Kristóf2020-01-101-6/+9
| | | | | | | | | Previously, when cluster_size was set to 0, it always worked as if the cluster size was 64. This commit fixes it in wave32 mode by changing to work as if the cluster size was set to 32. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: release saved resources in si_compute_do_clear_or_copyPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 9b331e462e5 ("radeonsi: use compute shaders for clear_buffer & copy_buffer") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_clear_12bytes_bufferPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 6c901f06752 ("radeonsi: use compute shader for clear 12-byte buffer") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_copy_imagePierre-Eric Pelloux-Prayer2020-01-101-0/+3
| | | | | Fixes: 1b25d340b79 ("radeonsi: use compute for resource_copy_region when possible") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_clear_render_targetPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 984fd735152 ("radeonsi: use compute for clear_render_target when possible") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_expand_fmaskPierre-Eric Pelloux-Prayer2020-01-101-0/+1
| | | | | Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_retile_dccPierre-Eric Pelloux-Prayer2020-01-101-0/+4
| | | | | | Fixes: 1f21396431a ("radeonsi: add support for displayable DCC for multi-RB chips") Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2330 Reviewed-by: Marek Olšák <[email protected]>
* main: fix coverity error in _mesa_program_resource_find_name()Samuel Iglesias Gonsálvez2020-01-101-1/+4
| | | | | | | | We did not take into account if name is NULL, so we could dereference a NULL pointer in strncmp() call. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* panfrost: Add negative lod bias supportIcecream952020-01-102-12/+14
| | | | Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl/drm: update UAPIGurchetan Singh2020-01-102-175/+1
| | | | | | | This seems to compile. Header copied over from drm-misc-next 7da5492739db. Acked-by: Eric Engestrom <[email protected]>
* lima: drop support for R8G8B8 formatVasily Khoruzhick2020-01-091-1/+0
| | | | | | | | | We can only sample from 24-bit packed format and can't render into it and it causes chromium-based browsers to fail when they create FBO with GL_RGB format. Drop R8G8B8 alltogether so mesa can promote it to RGBX format. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* anv: Re-use flush_descriptor_sets in flush_compute_stateJason Ekstrand2020-01-091-65/+25
| | | | | | | | | | There's no reason to hand-roll all of the memory re-allocation fall-back code for compute shaders. It's just duplicated complexity. This also makes it more clear in flush_compute_state where the MEDIA_INTERFACE_DESCRIPTOR_LOAD command gets emitted relative to other packets in the command stream. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Flag descriptors dirty when gl_NumWorkgroups is usedJason Ekstrand2020-01-091-1/+8
| | | | | Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* anv: Don't add dynamic state base address to push constants on Gen7Jason Ekstrand2020-01-091-14/+20
| | | | | | | | | | | | Because Gen7 push constants are already relative to dynamic state base address, they aren't really an address. It's deceptive to return an address from the helper function. Instead, let's leave it as a special-case in the gen7-11 helper; we don't need the helper for code de-duplication for Gen7 anyway. Fixes: 67d2cb3e9367a "anv: Add get_push_range_address() helper" Closes: #2323 Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* lima: add debug flag to disable tilingVasily Khoruzhick2020-01-103-1/+4
| | | | | | | | | Add debug flag to disable tiling. Note that it prevents lima from creating tiled buffers, but it's still able to import them if modifier is specified Reviewed-by: Andreas Baierl <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: use linear layout for shared buffers if modifier is not specifiedVasily Khoruzhick2020-01-101-1/+8
| | | | | | | | | | Use linear layout for shared buffers if modifier is not specified and use linear layout when importing buffers with invalid modifier. Fixes: 01a451b04d2d ("lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()") Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* glsl: call calculate_subroutine_compat() from the nir linkerTimothy Arceri2020-01-102-2/+2
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* glsl: move calculate_subroutine_compat() to shared linker codeTimothy Arceri2020-01-103-37/+41
| | | | | | We will make use of this in the nir linker in the following patch. Reviewed-by: Tapani Pälli <[email protected]>
* glsl: call uniform resource checks from the nir linkerTimothy Arceri2020-01-102-1/+2
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* glsl: move uniform resource checks into the common linker codeTimothy Arceri2020-01-103-80/+86
| | | | | | We will call this from the nir linker in the following patch. Reviewed-by: Tapani Pälli <[email protected]>
* glsl: call check_subroutine_resources() from the nir linkerTimothy Arceri2020-01-102-1/+2
| | | | Reviewed-by: Tapani Pälli <[email protected]>
* glsl: move check_subroutine_resources() into the shared util codeTimothy Arceri2020-01-103-15/+20
| | | | | | We will make use of this in the nir linker in the following patch. Reviewed-by: Tapani Pälli <[email protected]>
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-093-3/+0
|
* ir3: Set up full/half register conflicts correctlyKristian H. Kristensen2020-01-093-2/+31
| | | | | | | | | | | | | | Setting up transitive conflicts between a full register and its two half registers (eg r0.x and hr0.x and hr0.y) will make the half registers conflict. They don't actually conflict and this prevents us from using both at the same time. Add and use a new ra helper that sets up transitive conflicts between a register and its subregisters, except it carefully avoids the subregister conflict. Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* llvmpipe: add ARB_derivative_control supportDave Airlie2020-01-102-1/+5
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9Marek Olšák2020-01-095-4/+33
| | | | | | | Fixes: 69ea473 "amd/addrlib: update to the latest version" Closes: #2325 Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* anv: fix intel perf queries availability writesLionel Landwerlin2020-01-091-14/+5
| | | | | | | | | The availability is not written at the location changed in ee6fbb95a74d... Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: ee6fbb95a74d ("anv: Properly handle host query reset of performance queries") Reviewed-by: Jason Ekstrand <[email protected]>
* radeon/vcn: Handle crop parameters for encoderSatyajit Sahu2020-01-091-4/+11
| | | | | | | | | Set proper cropping parameter if frame cropping is enabled Signed-off-by: Satyajit Sahu <[email protected]> Reviewed-by: Boyuan Zhang [email protected] Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
* nir: fix printing of var_decl with more than 4 components.Daniel Schürmann2020-01-091-1/+1
| | | | | | | Reviewed-By: Timur Kristóf <[email protected]> Fixes: a8ec4082a41830cf67a4fd405402fd2d820722fd ('nir+vtn: vec8+vec16 support') Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3320>
* radv: advertise VK_AMD_shader_image_load_store_lodSamuel Pitoiset2020-01-092-0/+2
| | | | | | | This extension allows to use LOD with image read/write operations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* aco: handle nir_intrinsic_image_deref_{load,store} with lodSamuel Pitoiset2020-01-091-2/+17
| | | | | | | | | Use image_load_mip and image_store_mip respectively if the lod parameter isn't zero. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/llvm: handle nir_intrinsic_image_deref_{load,store} with lodSamuel Pitoiset2020-01-091-2/+10
| | | | | | | | Use image_load_mip and image_store_mip respectively if the lod parameter isn't zero. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv,nir: add new lod parameter to image_{load,store} intrinsicsSamuel Pitoiset2020-01-0910-2/+57
| | | | | | | | | | | | SPV_AMD_shader_image_load_store_lod allows to use a lod parameter with OpImageRead, OpImageWrite and OpImageSparseRead. According to the specification, this parameter should be a 32-bit integer. It is initialized to 0 when no lod parameter is found during SPIR-V->NIR translation. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* spirv: add SpvCapabilityImageReadWriteLodAMDSamuel Pitoiset2020-01-092-0/+5
| | | | | | | New SPIR-V capability for SPV_AMD_shader_image_load_store_lod. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* mesa: create program resource hash in a single placeTapani Pälli2020-01-094-6/+3
| | | | | | | | | This is a cleanup but also a fix for commit dd09f1d806b. In case of i965 we did not actually create hash for cached shader programs. Fixes: dd09f1d806b "mesa/st/i965: add a ProgramResourceHash for quicker resource lookup" Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: add support for ARB_indirect_parameters.Dave Airlie2020-01-092-2/+19
| | | | | | | | | This just adds support for getting the draw count from the indirect buffer. Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
* llvmpipe: enable driver side multi draw indirectDave Airlie2020-01-091-1/+2
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
* gallium/util: add multi_draw_indirect to util_draw_indirect.Dave Airlie2020-01-091-9/+13
| | | | | | | | ARB_indirect_parameters needs drivers to deal with mutli_draw_indirect themselves. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
* mesa: Prevent _MaxLevel from being less than zeroThong Thai2020-01-081-1/+1
| | | | | | | | | | When decoding using VDPAU, the _MaxLevel value becomes -1 due to NumLevels being equal to 0 at a certain point, and decoding fails due to an assertion later on. Signed-off-by: Thong Thai <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Cc: 19.2 19.3 <[email protected]>
* ac: add ac_build_s_endpgmMarek Olšák2020-01-082-0/+7
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: add 128-bit bitcountMarek Olšák2020-01-082-0/+12
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac/gpu_info: add pc_lines and use it in radeonsiMarek Olšák2020-01-083-1/+5
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: unify primitive export codeMarek Olšák2020-01-084-113/+78
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: unify build_sendmsg_gs_alloc_reqMarek Olšák2020-01-084-48/+31
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: clean up messy si_emit_rasterizer_prim_stateMarek Olšák2020-01-085-39/+30
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: determine accurately if line stippling is enabled for performanceMarek Olšák2020-01-083-4/+17
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 02:13:44 +0000