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* i965/fs: Handle V/UV immediates in dump_instructions()Matt Turner2018-12-101-0/+5
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* intel/compiler: Always print flag subregister numberSagar Ghuge2018-12-101-7/+6
| | | | | | | | | | While disassembling the predicate always print flag subregister number to keep grammar same across the generation for assembler tool. v2: Combine consecutive format calls (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
| | | | | | | | | | When RepCtrl is set, the swizzle field is ignored by the hardware. In order to ensure a 1-to-1 correspondence between the human-readable disassembly and the binary instruction encoding always set the swizzle to XXXX (all zeros) when it is unused due to RepCtrl Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* meson: Add nir_algebraic_parser_test to suitesDylan Baker2018-12-101-0/+1
| | | | | | | | Just to make it easier to run a nir tests together. Fixes: a0ae12ca91a45f81897e774019cde9bd081f03a0 ("nir/algebraic: Add unit tests for bitsize validation") Reviewed-by: Eric Engestrom <[email protected]>
* amd/addrlib: drop si_ci_vi_merged_enum.h from the listEmil Velikov2018-12-101-1/+0
| | | | | Fixes: 776b9113656 ("amd/addrlib: update Mesa's copy of addrlib") Signed-off-by: Emil Velikov <[email protected]>
* freedreno: add the missing _la in libfreedreno_ir3_laEmil Velikov2018-12-101-1/+1
| | | | | Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Signed-off-by: Emil Velikov <[email protected]>
* freedreno: drop duplicate MKDIR_GEN declarationEmil Velikov2018-12-101-1/+0
| | | | | Fixes: aa0fed10d35 ("freedreno: move ir3 to common location") Signed-off-by: Emil Velikov <[email protected]>
* loader: free error state, when checking the drawable typeKirill Burtsev2018-12-101-0/+1
| | | | | | | | | | | | | | Currently we distinguish if the drawable is a window or pixmap by checking xcb_present_select_input throws an error or not. Yet, we don't always free the error state returned by xcb. Cc: Kirill Burtsev <[email protected]> Cc: Boyan Ding <[email protected]> Fixes: 6bd9ba7d074 ("loader: Add dri3 helper") Reviewed-by: Emil Velikov <[email protected]> [Emil: add commit message, fixes tag] Signed-off-by: Emil Velikov <[email protected]>
* nir: make use of new nir_cf_list_clone_and_reinsert() helperTimothy Arceri2018-12-101-48/+28
| | | | | Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: add a new nir_cf_list_clone_and_reinsert() helperTimothy Arceri2018-12-101-0/+10
| | | | | Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: clarify some nit_loop_info member namesTimothy Arceri2018-12-103-17/+19
| | | | | | | | | Following commits will introduce additional fields such as guessed_trip_count. Renaming these will help avoid confusion as our unrolling feature set grows. Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: small tidy ups for nir_loop_analyze()Timothy Arceri2018-12-101-21/+10
| | | | | Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Flip arguments to load_register_reg helpers.Kenneth Graunke2018-12-095-9/+10
| | | | | | | | | load_register_imm and load_register_mem take the destination as the first argument, so I'd like load_register_reg to do the same the sake of consistency. Otherwise, reading sequences of mixed LRI/LRM/LRR is needlessly confusing. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Delete dead brw_meta_resolve_color prototype.Kenneth Graunke2018-12-091-7/+0
| | | | Dead since commit 09e041d61d367ff3a9e8492521606090050255d4 (May 2016).
* nv50/ir: fix use-after-free in ConstantFolding::visitKarol Herbst2018-12-091-33/+49
| | | | | | | | | | | opnd() might delete the passed in instruction, but it's used through i->srcExists() later in visit v2: use continue instead return v3: use brackets for the outer if/else chain Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nouveau: use atomic operations for driver statisticsKarol Herbst2018-12-091-3/+4
| | | | | | | multiple threads can write to those at the same time Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: initialize relDegree staticlyKarol Herbst2018-12-091-7/+16
| | | | | | | this race condition is pretty harmless, but also pretty trivial to fix Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* shader-packingEric Anholt2018-12-071-1/+2
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* tfuEric Anholt2018-12-071-1/+1
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* v3d: Fix a leak of the disassembled instruction string during debug dumps.Eric Anholt2018-12-071-0/+1
| | | | Fixes: ade416d02369 ("broadcom: Add VC5 NIR compiler.")
* vc4: Fix a leak of the transfer helper on screen destroy.Eric Anholt2018-12-071-0/+3
| | | | Fixes: d009463a6549 ("vc4: Switch to using u_transfer_helper for MSAA maps.")
* v3d: Fix a leak of the transfer helper on screen destroy.Eric Anholt2018-12-071-0/+2
| | | | Fixes: 7a30517cce8f ("broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.")
* v3d: Add VIR dumping of TMU config p0/p1.Eric Anholt2018-12-073-14/+33
| | | | I had a bit of it for V3D 3.x, but didn't update it for 4.x.
* v3d: Simplify VIR uniform dumping using a temporary.Eric Anholt2018-12-071-19/+10
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* v3d: Garbage collect unused uniforms code.Eric Anholt2018-12-072-90/+0
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* v3d: Split most of TEXTURE_SHADER_STATE setup out of sampler views.Eric Anholt2018-12-071-58/+69
| | | | For shader image load/store, we want most of this logic to be shared.
* v3d: Avoid confusing auto-indenting in TEXTURE_SHADER_STATE packingEric Anholt2018-12-071-4/+4
| | | | | Having "v3dx_pack() {" under each #if branch would confuse emacs's indenter.
* v3d: Fix handling of texture first_layer offsets for 3D textures.Eric Anholt2018-12-071-5/+5
| | | | | I think this bug predated adding v3d_layer_offset(). Noticed during an unrelated refactor.
* v3d: Return the right gl_SampleMaskIn[] value.Eric Anholt2018-12-073-11/+1
| | | | | It's supposed to be the dispatched sample mask for this pixel, not the GL state's sample mask.
* v3d: Fix a comment typoEric Anholt2018-12-071-1/+1
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* v3d: Convert to using nir_src_as_uint() from const_value derefs.Eric Anholt2018-12-071-14/+10
| | | | | Follows 16870de8a0aa ("nir: Use nir_src_is_const and nir_src_as_* in core code") to clean up v3d.
* v3d: Don't forget to flush writes to UBOs.Eric Anholt2018-12-072-5/+16
| | | | | If someone did TF into a UBO, we might have left the TF job un-flushed at the point of reading.
* v3d: Make an array for frag/vert texture state in the context.Eric Anholt2018-12-077-42/+21
| | | | | This simplifies a bunch of our texture handling, while introducing the slots necessary for adding new shader stages.
* v3d: Re-use the wrap mode uniform on V3D 3.3.Eric Anholt2018-12-071-24/+4
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* v3d: Put default vertex attribute values into the state uploader as well.Eric Anholt2018-12-073-8/+12
| | | | | The default attributes are long-lived (the state struct is cached), and only 256 bytes each.
* v3d: Create a state uploader for packing our shaders together.Eric Anholt2018-12-074-13/+35
| | | | | | Shaders are usually quite short, and are private to the context. We can save memory and reduce the work the kernel needs to do at exec time by packing them together in a stream uploader for long-lived state.
* v3d: Update simulator cache flushing code to match the kernel better.Eric Anholt2018-12-071-13/+19
| | | | | We were missing the invalidate between bin and render (possibly relevant for SSBOs), and still trying to flush the nonexistent L2C on 3.3+.
* v3d: Use the TFU to do generatemipmap.Eric Anholt2018-12-077-1/+175
| | | | | This is a separate, dedicated hardware unit for texture layout conversions and mipmap generation.
* v3d: Add the V3D TFU submit interface to the simulator.Eric Anholt2018-12-073-20/+90
| | | | | | | | | The TFU lets us format raster and SAND images into formats that can be read by the texture engine, and do mipmap generation. The UAPI comes from drm-next e69aa5f9b97f ("Merge tag 'drm-misc-next-2018-12-06' of git://anongit.freedesktop.org/drm/drm-misc into drm-next")
* v3d: Use combined input/output segments.Eric Anholt2018-12-074-5/+41
| | | | | | | The HW apparently has some issues (or at least a much more complicated VCM calculation) with non-combined segments, and the closed source driver also uses combined I/O. Until I get the last CTS failure resolved (which does look plausibly like some VPM stomping), let's use combined I/O too.
* v3d: Add missing OES_half_float_linear support.Eric Anholt2018-12-071-0/+1
| | | | | | | | We were exposing ARB_texture_float, but apparently not the OES subset flag. Fixes regression from GLES3 support to GLES2. Fixes: fcf9fcee3c8a ("mesa/main: do not require float-texture filtering for es3")
* v3d: Add support for RGBA_SRGB along with BGRA_SRGB.Eric Anholt2018-12-071-0/+2
| | | | | This is the actual native format for the hardware, without swizzling. Noticed while debugging why GLES3 disappeared.
* intel/blorp: Expand blorp_address::offset to be 64 bits.Kenneth Graunke2018-12-074-4/+4
| | | | | | | | | | | | | In the softpin world, surface state base address may be a fixed 64-bit address (with no associated BO). It makes sense to store this in the offset field. But it needs to be the full size. We also update the clear color address to be consistently uint64_t everywhere so we can continue passing intel_miptree_get_clear_color a pointer to the blorp_address's offset field without type mismatches. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* freedreno/drm: fix memory leakRob Clark2018-12-071-0/+3
| | | | | | | | Fix an emberrasing memory leak with the non-softpin submit/rb implementation. Fixes: f3cc0d27475 freedreno: import libdrm_freedreno + redesign submit Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: track max flow control depth for a5xx/a6xxRob Clark2018-12-075-4/+37
| | | | | | Rather than just hard-coding BRANCHSTACK size. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: code-motionRob Clark2018-12-076-838/+942
| | | | | | | Split up ir3_compiler_nir.c a bit before starting to add new stuff for a6xx SSBO/image instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sync instr/disasmRob Clark2018-12-074-25/+132
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't fetch unused tex componentsRob Clark2018-12-072-0/+29
| | | | | | | Detect when a component of an (for example) texture fetch is unused and propagate the updated wrmask back to the parent instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: blitter fixesRob Clark2018-12-072-3/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-12-077-35/+56
| | | | Signed-off-by: Rob Clark <[email protected]>
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