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* glsl: Refactor implicit conversion into its own helperAndres Gomez2016-08-051-80/+86
| | | | | | | | v2: Refactor also the conversion to constant and replacement code (Timothy). Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Andres Gomez <[email protected]>
* glsl/types: disallow implicit conversions before GLSL 1.20Andres Gomez2016-08-051-4/+4
| | | | | | | | | Implicit conversions were added in the GLSL 1.20 spec version. v2: Join the checks for GLSL 1.10 and ESSL (Timothy). Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Andres Gomez <[email protected]>
* i965: Rework the unlit centroid workaround.Kenneth Graunke2016-08-052-25/+33
| | | | | | | | | | | | | | | | | | | | | | | Previously, for every input, we moved the dispatch mask to the flag register, then emitted two predicated PLN instructions, one with centroid barycentric coordinates (for normal pixels), and one with pixel barycentric coordinates (for unlit helper pixels). Instead, we can simply emit a set of predicated MOVs at the top of the program which copy the pixel barycentric coordinates over the centroid ones for unlit helper pixel channels. Then, we can just use normal PLNs. On Sandybridge: total instructions in shared programs: 7538470 -> 7534500 (-0.05%) instructions in affected programs: 101268 -> 97298 (-3.92%) helped: 705 HURT: 9 (all of which are SIMD16 programs) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swr: [rasterizer core] static analysis fixes for conservative rastTim Rowley2016-08-042-5/+10
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] implement InnerConservative input coverageTim Rowley2016-08-046-182/+357
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] remove CanEarlyZ functionTim Rowley2016-08-041-6/+0
| | | | | | Test is now in SetupPipeline. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] use 32x32 macrotile for openswrTim Rowley2016-08-041-4/+4
| | | | | | Significant performance increase (up to 2x) on high geometry workloads. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer fetch] add support for 24bit format fetchTim Rowley2016-08-041-0/+1
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer fetch] additional fetch format supportTim Rowley2016-08-041-3/+15
| | | | | | | | Add support for 0 pitch in fetch. Add support for USCALE/SSCALE for 32bit integer fetches. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] fix potential jit exit crashTim Rowley2016-08-041-1/+6
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] update sync handlingTim Rowley2016-08-045-15/+15
| | | | | | | | Sync now uses a callback to ensure that it's called by the last thread moving past a DC. This will help with the new counter handling. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] rename variableTim Rowley2016-08-041-7/+7
| | | | | | Avoid nested declarations of the same name within a single function. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] adjust extern "C" block scopeTim Rowley2016-08-041-3/+5
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] conservative rast degenerate handlingTim Rowley2016-08-045-144/+332
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] allow hexadecimal for integer knobsTim Rowley2016-08-041-3/+6
| | | | Signed-off-by: Tim Rowley <[email protected]>
* mesa: Dynamically allocate the matrix stack.Eric Anholt2016-08-042-4/+25
| | | | | | | | | | | | | By allocating and initializing the matrices at context creation, the OS couldn't even overcommit the pages. This saves about 63k (out of 946k) of maximum memory size according to massif on simulated vc4 glsl-algebraic-add-add-1. It also means we could potentially relax the maximum stack sizes, but that should be a separate commit. v2: Drop redundant Top update, explain why the stack is small at init time. Reviewed-by: Brian Paul <[email protected]>
* state_tracker: Initialize the draw context only when needed.Eric Anholt2016-08-045-12/+36
| | | | | | | | | | | It's only used for rarely-used deprecated GL features (feedback/rasterpos), so we can skip the memory allocation and initialization for it most of the time. Saves about 659k (out of 1605k) of maximum memory size according to massif on simulated vc4 glsl-algebraic-add-add-1 Reviewed-by: Brian Paul <[email protected]>
* vc4: Move scalarizing and some lowering to link time.Eric Anholt2016-08-041-5/+12
| | | | | | | This works out to be a wash in terms of memory usage: We use more memory to store the separate ALU instructions, but we optimize out a lot of code as well. The main result, though, is that we do more of our work at link time rather than draw time.
* vc4: Avoid VS shader recompiles by keeping a set of FS inputs seen so far.Eric Anholt2016-08-043-25/+81
| | | | | | | | | | | | We don't want to bake the whole array into the FS key, because of the hashing overhead. But we can keep a set of the arrays seen, and use a pointer to the copy in as the array's proxy. Between this and the previous patch, gl-1.0-blend-func now passes on hardware, where previously it was filling the 256MB CMA area with shaders and OOMing. Drops 712 shaders from shader-db.
* vc4: Don't recompile the CS when the FS changes.Eric Anholt2016-08-041-0/+2
| | | | | | | The compiled_fs_id is a proxy for the vc4->prog.fs->input_slots[], but only the VS dereferences it. Drops 754 shaders from shader-db.
* vc4: Move FS inputs setup out to a helper function.Eric Anholt2016-08-041-34/+41
| | | | It's a pretty big block, and I was about to make it bigger.
* nir: Make nir_opt_remove_phis see through moves.Kenneth Graunke2016-08-041-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I found a shader in Tales of Maj'Eyal that contains: if ssa_21 { block block_1: /* preds: block_0 */ ...instructions that prevent the select peephole... vec1 32 ssa_23 = imov ssa_4 vec1 32 ssa_24 = imov ssa_4.y vec1 32 ssa_25 = imov ssa_4.z /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ vec1 32 ssa_26 = imov ssa_4 vec1 32 ssa_27 = imov ssa_4.y vec1 32 ssa_28 = imov ssa_4.z /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec1 32 ssa_29 = phi block_1: ssa_23, block_2: ssa_26 vec1 32 ssa_30 = phi block_1: ssa_24, block_2: ssa_27 vec1 32 ssa_31 = phi block_1: ssa_25, block_2: ssa_28 Here, copy propagation will bail because phis cannot perform swizzles, and CSE won't do anything because there is no dominance relationship between the imovs. By making nir_opt_remove_phis handle identical moves, we can eliminate the phis and rewrite everything to use ssa_4 directly, so all the moves become dead and get eliminated. I don't think we need to check "exact" - just the alu sources. Presumably phi sources should match in their exactness. On Broadwell: total instructions in shared programs: 11639872 -> 11638535 (-0.01%) instructions in affected programs: 134222 -> 132885 (-1.00%) helped: 338 HURT: 0 v2: Fix return value to be NULL, not false (caught by Iago). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Make nir_alu_srcs_equal non-static.Kenneth Graunke2016-08-042-1/+4
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Turn imov/fmov of undef into undef.Kenneth Graunke2016-08-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | On Broadwell: total instructions in shared programs: 11640214 -> 11639872 (-0.00%) instructions in affected programs: 17744 -> 17402 (-1.93%) helped: 78 HURT: 0 total spills in shared programs: 2924 -> 2922 (-0.07%) spills in affected programs: 104 -> 102 (-1.92%) helped: 1 HURT: 0 total fills in shared programs: 4394 -> 4389 (-0.11%) fills in affected programs: 237 -> 232 (-2.11%) helped: 1 HURT: 0 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Use a separate register for every access to an SSA undef.Kenneth Graunke2016-08-042-13/+11
| | | | | | | | | | | | | | | | | | | | | | Previously, we allocated a new VGRF for every undefined definition. Instead, this patch makes us allocate a new VGRF for every use of an undefined definition. This makes sure that undefined values are fully independent of one another, and have live ranges limited to their single use. This allows register coalescing to combine the source and destination of MOVs from undefined sources, eliminating the MOV altogether. On Broadwell: total instructions in shared programs: 11641187 -> 11640214 (-0.01%) instructions in affected programs: 70199 -> 69226 (-1.39%) helped: 213 HURT: 1 v2: Add a comment (based on Iago's suggested one). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* vl/dri3: Destroy Present event context when destroying drawable v2Michel Dänzer2016-08-041-5/+16
| | | | | | | | | | | Without this, the X server may accumulate stale Present event contexts if a client performs several video decoding sessions using the same window. v2: Based on Chris Wilson's review: * Use xcb_discard_reply() instead of free(xcb_request_check()) Reviewed-and-Tested-by: Leo Liu <[email protected]>
* loader/dri3: Destroy Present event context when destroying drawable v2Michel Dänzer2016-08-041-1/+7
| | | | | | | | | | | Without this, the X server may accumulate stale Present event contexts if a client ends up creating and destroying DRI drawables for the same window. v2: Based on Chris Wilson's review: * Use xcb_present_select_input_checked so that protocol errors generated by old X servers can be handled gracefully * Use xcb_discard_reply() instead of free(xcb_request_check())
* gbm: Correct bo_import documentation (trivial)Ben Widawsky2016-08-031-1/+1
| | | | | | | | | | | | | | Missed here: commit a43d286ef7ff65087b1f051d071b829ca7b02073 Author: Kristian Høgsberg <[email protected]> Date: Fri Mar 28 10:17:11 2014 -0700 gbm: Add import from fd Cc: Kristian Høgsberg <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* vc4: Avoid generating a custom shader per level in glGenerateMipmaps().Eric Anholt2016-08-033-7/+25
| | | | | | | | | | We were baking in the LOD of the source level to each shader. Instead, pass it in as a uniform -- this requires storing it to a temp register, but that's better than compiling a ton of separate shaders: total instructions in shared programs: 115032 -> 115036 (0.00%) instructions in affected programs: 96 -> 100 (4.17%) LOST: 572
* vc4: Tell valgrind about BO allocations from mmap time to destroy.Eric Anholt2016-08-032-0/+11
| | | | | | This helps in debugging memory pressure. It would be nice if we could tell valgrind about it all the way from allocation time to destroy, but we need a pointer to hand to VALGRIND_MALLOCLIKE_BLOCK.
* loader: fix memory leak in loader_dri3_openJan Ziak2016-08-031-0/+1
| | | | | | | | | Found via "valgrind --leak-check=full glxgears". Signed-off-by: Jan Ziak (http://atom-symbol.net) <[email protected]> Acked-by: Boyan Ding <[email protected]> Cc: "12.0 11.2" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Fix a leak of the src[] array of VPM reads in optimization.Eric Anholt2016-08-031-4/+5
| | | | Cc: "12.0" <[email protected]>
* vc4: Fix leak of the bo_handles table.Eric Anholt2016-08-031-0/+1
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* vc4: Fix handling of UBO range offsets.Eric Anholt2016-08-031-2/+3
| | | | | | The ranges are in units of bytes, not dwords. This wasn't caught by piglit tests because ttn tends to make one big uniform file, so we only had one UBO range with a src and dst offset of 0.
* nir: Allow opt_peephole_select to work on empty blocks.Eric Anholt2016-08-031-7/+0
| | | | | | | | | | | | | | nir_opt_peephole_select has the job of removing IF statements with no side effects. However, if the IF statement's successor didn't have any instructions in it, we were skipping it, which occurred in mupen64 on vc4 with glsl_to_nir enabled: instructions in affected programs: 6134 -> 4120 (-32.83%) total uniforms in shared programs: 38268 -> 38219 (-0.13%) No changes on Haswell shader-db. Reviewed-by: Jason Ekstrand <[email protected]>
* vc4: Dump NIR at shader state creation time as well.Eric Anholt2016-08-031-0/+8
| | | | I keep wanting to see this version of the NIR.
* r600g: use last_gfx_fence like radeonsiMarek Olšák2016-08-031-3/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: move last_gfx_fence from radeonsi to common codeMarek Olšák2016-08-035-7/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: skip unnecessary si_update_shaders callsMarek Olšák2016-08-034-7/+27
| | | | | | Small decrease in draw call overhead. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: print the command line to VM fault reports (v2)Marek Olšák2016-08-031-0/+3
| | | | | | v2: rebase on top of Brian's commit Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: print the command line to all logs (v2)Marek Olšák2016-08-031-0/+4
| | | | | | | | for piglit with the pipelined hang detection mode v2: rebase on top of Brian's commit Reviewed-by: Nicolai Hähnle <[email protected]>
* ddebug: don't use fmemopen on non-Linux OSMarek Olšák2016-08-031-0/+5
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97140 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't set the last parameter component of llvm.AMDGPU.cubeMarek Olšák2016-08-031-2/+8
| | | | | | LLVM doesn't use it. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use llvm.amdgcn.cube* if availableMarek Olšák2016-08-031-4/+28
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use llvm.amdgcn.rsq.f64 if availableMarek Olšák2016-08-031-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use v_mad_f32 for fmaMarek Olšák2016-08-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | v_fma_f32 runs at FP64 rate (= slow). Alien Isolation and F1 2015 seem to use fma for all d3d multiply-add instructions, which is silly. This tries to restore performance for those games. The main difference between v_mad_f32 and v_fma_f32 is that v_mad doesn't support denormals, which we don't enable anyway, because they are slow too. Also, there is code size reduction: Totals from affected shaders: VGPRS: 109796 -> 109808 (0.01 %) Spilled SGPRs: 29995 -> 30022 (0.09 %) Spilled VGPRs: 12 -> 13 (8.33 %) <-- it's just one shader going from 12 to 13 Code Size: 6667596 -> 6476356 (-2.87 %) bytes Max Waves: 26931 -> 26899 (-0.12 %) I've not actually tested real performance. Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: use mt->offset in intel_miptree_map_movntdqa()Haixia Shi2016-08-031-0/+3
| | | | | | | | | | | We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi <[email protected]> Cc: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63
* nir: fix validation messageTimothy Arceri2016-08-031-2/+2
| | | | | | | Looks like a copy and paste error from f752effa087 Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* swr: build swr with -fno-strict-aliasingTim Rowley2016-08-021-0/+1
| | | | | | | swr rasterizer contains numerous data transfers between vectors and ordinary C types. Fixing for strict aliasing will take time. Reviewed-by: Matt Turner <[email protected]>
* ast: Updated AST_NUM_OPERATORS for coherence with ast_operatorsAndres Gomez2016-08-022-9/+10
| | | | | | | | | | | | | | | AST_NUM_OPERATORS stores the dimension of the ast_operators enumeration but was not updated after its last modification. This doesn't add any real modification for any code paths but it makes sense for coherence. v2 (Eric Engestrom): Just place the define at the end of the enumeration, not below. Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
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