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* radv: rename radv_cmd_buffer_flush_state() to radv_draw()Samuel Pitoiset2017-10-201-59/+51
* radv: emit primitive restart from radv_emit_draw_registers()Samuel Pitoiset2017-10-201-29/+30
* radv: add radv_emit_draw_registers()Samuel Pitoiset2017-10-201-12/+34
* radv: refactor indirect draws (+count buffer) with radv_draw_infoSamuel Pitoiset2017-10-201-103/+48
* radv: refactor indirect draws with radv_draw_infoSamuel Pitoiset2017-10-201-75/+133
* radv: refactor simple and indexed draws with radv_draw_infoSamuel Pitoiset2017-10-201-68/+118
* radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite itSamuel Pitoiset2017-10-201-2/+11
* radv: clear the dirty flags in the corresponding emit helpersSamuel Pitoiset2017-10-201-2/+8
* radv: rename RADV_CMD_DIRTY_RENDER_TARGETS to RADV_CMD_DIRTY_FRAMEBUFFERSamuel Pitoiset2017-10-202-3/+3
* radv: move DB_COUNT_CONTROL initialization to si_emit_config()Samuel Pitoiset2017-10-202-1/+5
* i965/vec4: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-202-21/+0
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* nir: set default lod to texture opcodes that needed it but don't provide itSamuel Iglesias Gonsálvez2017-10-201-0/+13
* radv: enable GS on GFX9Bas Nieuwenhuizen2017-10-201-3/+1
* radv: calculate and emit GFX9 GS registers to pipeline state.Bas Nieuwenhuizen2017-10-204-7/+158
* ac/nir: Fix up GS input vgprs.Bas Nieuwenhuizen2017-10-201-0/+15
* ac/nir: Add loading from LDS for merged GS.Bas Nieuwenhuizen2017-10-201-15/+21
* ac/nir: Add ES output to LDS for GFX9.Bas Nieuwenhuizen2017-10-201-8/+49
* ac/nir: Add merged GS function.Bas Nieuwenhuizen2017-10-201-17/+63
* radv: Only emit TES when it exists.Bas Nieuwenhuizen2017-10-201-4/+6
* radv: Use control shader presence for detecting tess.Bas Nieuwenhuizen2017-10-201-1/+1
* radv: fixup tess eval shader when combined.Dave Airlie2017-10-202-6/+23
* radv: Set VGT_GS_MODE properly for gfx9Bas Nieuwenhuizen2017-10-201-4/+7
* radv: ensure correct outinfo is picked.Dave Airlie2017-10-201-13/+14
* swr: Rework scratch space allocationGeorge Kyriazis2017-10-192-30/+23
* radv: Enable tessellation shaders for GFX9.Bas Nieuwenhuizen2017-10-201-1/+1
* ac/nir: init full exec mask for merged shaders.Dave Airlie2017-10-203-0/+12
* radv: drop unused r600_htile_info.Dave Airlie2017-10-201-9/+0
* radv: fix CLEAR_STATE packet length.Dave Airlie2017-10-191-1/+1
* meson: don't build gallium dri target if gallium is disabledDylan Baker2017-10-191-1/+1
* radv: copy indirect lowering settings from radeonsiTimothy Arceri2017-10-201-1/+26
* radv: stop redundant setting of active_stagesTimothy Arceri2017-10-201-2/+0
* ac: move some code out of loop in store_tcs_output()Timothy Arceri2017-10-201-5/+5
* radv: Modify rsrc1/rsrc2 generation for merged tess.Bas Nieuwenhuizen2017-10-191-7/+16
* radv: Set correct registers for merged shader rings.Bas Nieuwenhuizen2017-10-191-12/+24
* radv: Add GFX9 HS emitting code.Bas Nieuwenhuizen2017-10-191-5/+16
* radv: Remove remaining hard coded references to VS.Bas Nieuwenhuizen2017-10-193-7/+28
* radv: Update GFX9 user data regs for GS/tess.Bas Nieuwenhuizen2017-10-194-14/+25
* radv: Add code to compile merged shaders.Bas Nieuwenhuizen2017-10-194-13/+39
* ac/nir: Add LS-HS input VGPR workaround.Bas Nieuwenhuizen2017-10-191-0/+18
* ac/nir: Compile the bodies of multiple shaders.Bas Nieuwenhuizen2017-10-191-50/+83
* ac/nir: Expand user SGPR descriptions a bit.Bas Nieuwenhuizen2017-10-191-3/+3
* ac/nir: Don't write to the dynamic HS word on GFX9.Bas Nieuwenhuizen2017-10-191-11/+16
* ac/nir: Add function creation for merged LS+HS.Bas Nieuwenhuizen2017-10-191-76/+178
* ac/nir: Make scan_shader_output_decl less dependent on the context.Bas Nieuwenhuizen2017-10-191-14/+17
* ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.Bas Nieuwenhuizen2017-10-191-1/+1
* ac/nir: Change interface to allow multiple source shaders.Bas Nieuwenhuizen2017-10-193-39/+48
* ac/nir: Add HS calling convention.Bas Nieuwenhuizen2017-10-191-1/+4
* ac: Parse the new HS RSRC1 register.Bas Nieuwenhuizen2017-10-191-0/+1
* swr: knob overrides for Intel Xeon PhiTim Rowley2017-10-195-1/+37