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* intel/fs,vec4: Properly account SENDs in IVB memory fenceCaio Marcelo de Oliveira Filho2020-04-204-8/+20
| | | | | | | | | | | Change brw_memory_fence to return the number of messages emitted, and use that to update the send_count statistic in code generation. This will fix the book-keeping for IVB since the memory fences will result in two SEND messages. Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4646>
* aco: move src1 to vgpr instead of using VOP3 for VOP2 instructions during iselDaniel Schürmann2020-04-201-9/+1
| | | | | | | | | Is simpler and helps a couple of shaders. Totals from affected shaders: (Vega) Code Size: 16341296 -> 16335460 (-0.04 %) bytes Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
* aco: fix 64bit fsubDaniel Schürmann2020-04-201-1/+1
| | | | | | | | Fixes: 425558bfd595ed3a7a049ad0f47a46b8b3c4691e ('aco: use v_subrev_f32 for fsub with an sgpr operand in src1') Reviewed-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4642>
* gtest: Update to 1.10.0Erik Faye-Lund2020-04-2041-12051/+6022
| | | | | Acked-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4576>
* nir/opt_algebraic: lower 64-bit fmin3/fmax3/fmed3Samuel Pitoiset2020-04-201-0/+4
| | | | | | | | | | | | | This unconditionally lowers 64-bit fmin3/fmax3/fmed3 because AMD hardware doesn't have native instructions, and no drivers except RADV uses these instructions. Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.f64.* with ACO. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
* nir/lower_int64: lower imin3/imax3/umin3/umax3/imed3/umed3Samuel Pitoiset2020-04-201-0/+18
| | | | | | | | | | Fixes dEQP-VK.spirv_assembly.instruction.amd_trinary_minmax.*.i64.* with ACO because this backend compiler expects most of the 64-bit operations to be lowered. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4570>
* radeonsi: skip vs output optimizations for some outputsPierre-Eric Pelloux-Prayer2020-04-204-2/+18
| | | | | | | | | | If PT_SPRITE_TEX is enabled, PS inputs are overriden at runtime so we can't apply the vs output optim. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2747 Fixes: 3ec9975555d ("radeonsi: eliminate trivial constant VS outputs") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4559>
* nir/gcm: dont move movs unless we can replace them later with their srcTimothy Arceri2020-04-201-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This helps us avoid moving the movs outside if branches when there src can't be scalarized. For example it avoids: vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler), if ... { r0 = imov ssa_7.z r1 = imov ssa_7.y r2 = imov ssa_7.x r3 = imov ssa_7.w ... } else { ... if ... { r0 = imov ssa_7.x r1 = imov ssa_7.w ... else { r0 = imov ssa_7.z r1 = imov ssa_7.y ... } r2 = imov ssa_7.x r3 = imov ssa_7.w } ... vec4 32 ssa_36 = vec4 r0, r1, r2, r3 Becoming something like: vec4 32 ssa_7 = tex ssa_6 (coord), 0 (texture), 0 (sampler), r0 = imov ssa_7.z r1 = imov ssa_7.y r2 = imov ssa_7.x r3 = imov ssa_7.w if ... { ... } else { if ... { r0 = imov r2 r1 = imov r3 ... else { ... } ... } While this is has a smaller instruction count it requires more work for the same result. With more complex examples we can also end up shuffling the registers around in a way that requires more registers to use as temps so that we don't overwrite our original values along the way. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: be more conservative about moving instructions from loopsTimothy Arceri2020-04-201-1/+15
| | | | | | | | | Here we only pull instructions further up control flow if they are constant or texture instructions. See the code comment for more information. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: allow derivative dependent intrinisics to be moved earlierTimothy Arceri2020-04-201-7/+14
| | | | | | | | | | | | We can't move them later as we could move them into non-uniform control flow, but moving them earlier should be fine. This helps avoid a bunch of spilling in unigine shaders due to moving the tex instructions sources earlier (outside if branches) but not the instruction itself. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Prefer the instruction's original blockJason Ekstrand2020-04-201-0/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Delete dead instructionsJason Ekstrand2020-04-201-3/+26
| | | | | | | | | | | | | | | Classically, global code motion is also a dead code pass. However, in the initial implementation, the decision was made to place every instruction and let conventional DCE clean up the dead ones. Because any uses of a dead instruction are unreachable, we have no late block and the dead instructions are always scheduled early. The problem is that, because we place the dead instruction early, it pushes the placement of any dependencies of the dead instruction earlier than they may need to be placed. In order prevent dead instructions from affecting the placement of live ones, we need to delete them. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Add a real concept of "progress"Jason Ekstrand2020-04-201-4/+11
| | | | | | | | | Now that the GCM pass is more conservative and only moves instructions to different blocks when it's advantageous to do so, we can have a proper notion of what it means to make progress. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Move block choosing into a helper functionJason Ekstrand2020-04-201-11/+21
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Use an array for storing the early blockJason Ekstrand2020-04-201-12/+40
| | | | | | | | | | We are about to adjust our instruction block assignment algorithm and we will want to know the current block that the instruction lives in. In order to allow for this, we can't overwrite nir_instr::block in the early scheduling pass. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/gcm: Loop over blocks in pin_instructionsJason Ekstrand2020-04-201-63/+58
| | | | | | | Now that we have the new block iterators, we can simplify things a bit. Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* nir/dominance: Better handle unreachable blocksJason Ekstrand2020-04-202-8/+38
| | | | | | | v2: Fix minor comments (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4636>
* aco: use v_subrev_f32 for fsub with an sgpr operand in src1Daniel Schürmann2020-04-191-1/+1
| | | | | | | | This fixes an accidentally introduced regression. Fixes: 9be4be515f2a08b9c9e5ae1fc4c5dc9a830c2337 ('aco: implement 16-bit nir_op_fsub/nir_op_fadd') Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4633>
* nir: Lower returns correctly inside nested loopsArcady Goldmints-Orlov2020-04-191-1/+1
| | | | | | | | | | | | | | | Inside nested flow control, nir_lower_returns inserts predicated breaks in the outer block. However, it would omit doing this if the remainder of the outer block (after the inner block) was empty. This is not correct in the case of loops, as execution just wraps back around to the start of the loop, so this change doesn't skip the predication inside loops. Fixes: 79dec93ead6e (nir: Add return lowering pass) Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2724 Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4603>
* anv: Apply any needed PIPE_CONTROLs before emitting stateJason Ekstrand2020-04-191-0/+12
| | | | | | | | | | | | | Push constants in particular can get picked up by the hardware at weird times that happen *before* 3DPRIMITIVE. Therefore, we need to flush before we emit all our state to ensure that any data they may pick up is in memory in time. This fixes an app which does vkCmdCopyBuffers immediately followed by a vkCmdBeginRenderPass and vkCmdDraw which uses the destination of the copy as a UBO which we push. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
* anv: Move vb_emit setup closer to where it's used in flush_stateJason Ekstrand2020-04-191-4/+4
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4601>
* Fix promotion of floats to doublesAlbert Astals Cid2020-04-1812-34/+34
| | | | | | | | | Use the f variants of the math functions if the input parameter is a float, saves converting from float to double and running the double variant of the math function for gaining no precision at all Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3969>
* ir3/ra: Fix off-by-one issues with live-range extensionConnor Abbott2020-04-183-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intersects() function assumes that inside each instruction values always die before they are defined, so that if the end of one range is the same instruction as the beginning of the next then they don't intersect. However, this isn't the case for values that become live at the beginning of a basic block, which become live *before* the first instruction, or instructions that die at the end of a basic block which die after the last instruction. For example, imagine that we have two values, A which is defined earlier in the block and B which is defined in the last instruction of the block and both die at the end of the basic block (e.g. are used in the next iteration of a loop). We would compute a range for A of, say, (10, 20) and for B of (20, 20) since each block's end_ip is the same as the ip of the last instruction, and RA would consider them to not interfere. There's a similar problem with values that become live at the beginning. The fix is to offset the block's start_ip and end_ip by one so that they don't correspond to any actual instruction. One way to think about this is that we're adding fake instructions at the beginning and end of a block where values become live & die. We could invert the order, so that values consumed by each instruction are considered dead at the end of the previous instruction, but then values that become dead at the beginning of the basic block would incorrectly have an empty live range, with a similar problem at the end of the basic block if we try to say that values are defined at the beginning of the next instruction. So the extra padding instructions are unavoidable. This fixes an accidental infinite loop in the shader for dEQP-VK.spirv_assembly.type.scalar.u32.switch_vert. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4614>
* util/sparse_free_list: manipulate node pointers using atomic primitivesLionel Landwerlin2020-04-181-4/+4
| | | | | | | | | | Probably doesn't fix anything but those should be accessed in an atomic way just like the head pointer. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: e4f01eca3b3cd1 ("util: Add a free list structure for use with util_sparse_array") Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4613>
* glsl: only set stage ref when uniforms referenced in stageTimothy Arceri2020-04-181-7/+215
| | | | | | | | | This updates the NIR uniform linker to behave like the GLSL IR linker and fixes a number of CTS tests once we enable the NIR linker for glsl. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: pull mark_array_elements_referenced() out into common helperTimothy Arceri2020-04-185-121/+130
| | | | | | | | We will reuse this helper in the NIR linker in the following patches. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: fix block index in NIR uniform linkerTimothy Arceri2020-04-181-1/+7
| | | | | | | | We only want to set the index for the first block of an array. Also add a comment about why we do not break here. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: error check max user assignable uniform locationsTimothy Arceri2020-04-181-0/+18
| | | | | | | This adds the error check to the NIR uniform linker. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: fix explicit locations for the glsl linkerTimothy Arceri2020-04-181-5/+16
| | | | | | | We already reserved explicit locations in the GLSL linker. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* Revert "glsl: fix resizing of the uniform remap table"Timothy Arceri2020-04-181-8/+4
| | | | | | | | | This reverts commit e0aa0a839f9c168784a1f50013c83877cc876094. Instead we fix it correctly in the following patch. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: tidy up uniform storage value count code in NIR linkerTimothy Arceri2020-04-181-8/+6
| | | | | | | | This makes the code cleaner and better reflects what the existing glsl IR linker does possibly fixing subtle bugs. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* glsl: fix struct offsets in the nir uniform linkerTimothy Arceri2020-04-181-3/+76
| | | | | | | | This change properly applies layouts to structs of uniforms in a similar way to the GLSL IR linker. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* nir: add matrix_layout to nir_variable dataTimothy Arceri2020-04-182-0/+6
| | | | | | | This will be used by the following patch. Reviewed-by: Alejandro Piñeiro <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4623>
* anv: skip writing perfcntr in results on Gen12+Lionel Landwerlin2020-04-181-0/+4
| | | | | | | | | | | | We were not capturing the register already so don't bother writing the delta in the results (we were previously doing a delta between two 0 values). v2: Fix unused function warning Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
* intel/perf: Enable MDAPI queries for Gen12Lionel Landwerlin2020-04-182-5/+8
| | | | | | | | | | We're missing the cases for gen12 leading to those metrics going missing. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 15b7b56eb2fb41 ("intel/perf: add TGL support") Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4586>
* pan/bit: Add fp16 min/max testsAlyssa Rosenzweig2020-04-171-8/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add constants testAlyssa Rosenzweig2020-04-171-0/+29
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add fexp2_fast testAlyssa Rosenzweig2020-04-171-3/+17
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add fexp2_fast interpAlyssa Rosenzweig2020-04-171-1/+8
| | | | | | | Kind of a hack and not at all how the h/w does it. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add FMA_MSCALE testAlyssa Rosenzweig2020-04-171-0/+29
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: _MSCALE interpAlyssa Rosenzweig2020-04-171-0/+11
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add BI_TABLE testAlyssa Rosenzweig2020-04-171-0/+17
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add log2 helper interpAlyssa Rosenzweig2020-04-171-0/+13
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add FMA_REDUCE testAlyssa Rosenzweig2020-04-171-0/+16
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add BI_REDUCE_FMA interpAlyssa Rosenzweig2020-04-171-0/+15
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add frexp_log testAlyssa Rosenzweig2020-04-171-1/+17
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bit: Add FREXP interp supportAlyssa Rosenzweig2020-04-171-1/+34
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bi: Lower special ops to 32-bitAlyssa Rosenzweig2020-04-171-0/+6
| | | | | | | | We don't have 16-bit tables. We could probably do a bit better to avoid so many conversions but hey. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bi: Round constants to 32-bitAlyssa Rosenzweig2020-04-171-1/+1
| | | | | | | We can only access lo/hi at 32-bit intervals. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
* pan/bi: Dump extra bits for disasmAlyssa Rosenzweig2020-04-171-0/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4615>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 00:36:05 +0000