mesa.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	radv: disable implicit sync for radv allocated bos v3	Andres Rodriguez	2017-10-21	4	-1/+8
*	radv: factor out radv_alloc_memory	Andres Rodriguez	2017-10-21	2	-5/+25
*	radv: Expose VK_EXT_global_priority	Andres Rodriguez	2017-10-21	4	-0/+5
*	radv: don't skip PS/VS partial flush	Andres Rodriguez	2017-10-21	1	-8/+6
*	radv: Implement VK_EXT_global_priority	Andres Rodriguez	2017-10-21	4	-8/+62
*	radeonsi: hardcode shader WAVE_LIMIT to the maximum value	Andres Rodriguez	2017-10-21	1	-7/+14
*	radv: hardcode shader WAVE_LIMIT to the maximum value	Andres Rodriguez	2017-10-21	1	-9/+18
*	vulkan: update headers & registry to VK 1.0.63	Andres Rodriguez	2017-10-21	1	-84/+180
*	broadcom/vc5: Use SETMSF to handle discards.	Eric Anholt	2017-10-20	2	-25/+12
*	broadcom/vc5: Set the snorm/unorm packing functions to be lowered.	Eric Anholt	2017-10-20	1	-0/+4
*	broadcom/vc5: Fix pasteo that broke vertex texturing.	Eric Anholt	2017-10-20	1	-1/+1
*	broadcom/vc5: Move default attribute value setup to the CSO and fix them.	Eric Anholt	2017-10-20	3	-29/+23
*	broadcom/vc5: Move most of the shader state attribute record to the CSO.	Eric Anholt	2017-10-20	4	-65/+90
*	broadcom/vc5: Fix build failure frm nir_shader::stage removal.	Eric Anholt	2017-10-20	1	-4/+4
*	i965/fs: Use align1 mode on ternary instructions on Gen10+	Matt Turner	2017-10-20	1	-4/+8
*	i965: Add align1 ternary instruction emission support	Matt Turner	2017-10-20	1	-55/+160
*	i965: Add align1 ternary instruction disassembler support	Matt Turner	2017-10-20	2	-75/+288
*	i965: Add align1 ternary instruction-word support	Matt Turner	2017-10-20	1	-0/+108
*	i965: Add align1 ternary instruction support to conversion functions	Matt Turner	2017-10-20	4	-34/+101
*	i965: Add align1 ternary instruction field encodings	Matt Turner	2017-10-20	1	-0/+35
*	i965: Add functions to abstract access to 3src register types	Matt Turner	2017-10-20	2	-20/+23
*	i965: Rename brw_inst's functions that access the 3src register type	Matt Turner	2017-10-20	3	-18/+18
*	i965: Rename brw_inst 3src functions in preparation for align1	Matt Turner	2017-10-20	4	-86/+92
*	i965: Print subreg in units of type-size on ternary instructions	Matt Turner	2017-10-20	1	-5/+26
*	i965: Add functions for brw_reg_type <-> hw 3src type	Matt Turner	2017-10-20	2	-0/+58
*	i965: Move brw_reg_type_is_floating_point to brw_reg_type.h	Matt Turner	2017-10-20	2	-13/+15
*	nir: Get rid of nir_shader::stage	Jason Ekstrand	2017-10-20	50	-187/+193
*	radv: use optimal packet order for draws	Samuel Pitoiset	2017-10-20	1	-17/+79
*	radv: add radv_emit_shaders_prefetch()	Samuel Pitoiset	2017-10-20	1	-12/+19
*	radv: add radv_emit_shader_prefetch()	Samuel Pitoiset	2017-10-20	1	-25/+23
*	st/mesa: correct a u_vbuf comment	Marek Olšák	2017-10-20	1	-3/+5
*	etnaviv: fix implicit conversion warning	Christian Gmeiner	2017-10-20	2	-2/+2
*	etnaviv: enable occlusion query if GPU supports it	Christian Gmeiner	2017-10-20	1	-1/+2
*	etnaviv: add support for occlusion queries	Christian Gmeiner	2017-10-20	1	-0/+78
*	etnaviv: add basic infrastructure for hw queries	Christian Gmeiner	2017-10-20	6	-0/+292
*	etnaviv: update headers from rnndb	Christian Gmeiner	2017-10-20	5	-89/+622
*	i965: Report supported context priorities to EGL/DRI	Chris Wilson	2017-10-20	1	-0/+13
*	i965: Pass the EGL/DRI context priority through to the kernel	Chris Wilson	2017-10-20	3	-0/+46
*	i965: Record the presence of the kernel scheduler	Chris Wilson	2017-10-20	1	-0/+11
*	egl,dri: Propagate context priority hint to driver->CreateContext	Chris Wilson	2017-10-20	15	-30/+71
*	egl: Support IMG_context_priority	Chris Wilson	2017-10-20	5	-0/+71
*	radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BIT	Fredrik Höglund	2017-10-20	1	-2/+1
*	radv: mark total_count as MAYBE_UNUSED in CmdSet{Viewport,Scissor}	Samuel Pitoiset	2017-10-20	1	-2/+2
*	radv: rename radv_cmd_buffer_flush_state() to radv_draw()	Samuel Pitoiset	2017-10-20	1	-59/+51
*	radv: emit primitive restart from radv_emit_draw_registers()	Samuel Pitoiset	2017-10-20	1	-29/+30
*	radv: add radv_emit_draw_registers()	Samuel Pitoiset	2017-10-20	1	-12/+34
*	radv: refactor indirect draws (+count buffer) with radv_draw_info	Samuel Pitoiset	2017-10-20	1	-103/+48
*	radv: refactor indirect draws with radv_draw_info	Samuel Pitoiset	2017-10-20	1	-75/+133
*	radv: refactor simple and indexed draws with radv_draw_info	Samuel Pitoiset	2017-10-20	1	-68/+118
*	radv: re-emit VGT_INDEX_TYPE because non-indexed draws overwrite it	Samuel Pitoiset	2017-10-20	1	-2/+11