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* isl: remove the cache line size alignment requirementSamuel Iglesias Gonsálvez2019-02-201-14/+0
* radv: Clean up a bunch of compiler warnings.Bas Nieuwenhuizen2019-02-203-7/+0
* radv: Sync ETC2 whitelisted devices.Bas Nieuwenhuizen2019-02-203-5/+11
* st/nir: use NIR for asm programsTimothy Arceri2019-02-192-1/+61
* st/mesa: Copy VP TGSI tokens if they exist, even for NIR shaders.Kenneth Graunke2019-02-191-2/+8
* radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpowKenneth Graunke2019-02-192-1/+4
* radeonsi/nir: set shader_buffers_declared properlyTimothy Arceri2019-02-201-10/+22
* radeonsi/nir: set colors_read properlyTimothy Arceri2019-02-201-7/+10
* radeonsi/nir: set input_usage_mask properlyTimothy Arceri2019-02-201-11/+36
* radeonsi/nir: Use uniform location when calculating const_file_max.Timur Kristóf2019-02-201-6/+6
* drirc: Add sddm-greeter to adaptive_sync blacklist.Mario Kleiner2019-02-191-0/+3
* driconf: add Civ6Sub executable for Civilization 6Marek Olšák2019-02-191-0/+6
* radeonsi: always enable NIR for Civilization 6 to fix corruptionMarek Olšák2019-02-191-0/+3
* radeonsi: add driconf option radeonsi_enable_nirMarek Olšák2019-02-193-1/+8
* mesa: Align doubles to a 64-bit starting boundary, even if packing.Kenneth Graunke2019-02-191-2/+6
* compiler: Make is_64bit(GL_*) helper more broadly availableKenneth Graunke2019-02-192-26/+33
* tegra/autotools: add missing libdrm cflagsEric Engestrom2019-02-191-0/+1
* tegra/meson: add missing dep_libdrmEric Engestrom2019-02-191-0/+1
* ac/nir: implement half-float nir_op_ldexpRhys Perry2019-02-191-1/+3
* ac/nir: implement half-float nir_op_frsqRhys Perry2019-02-191-2/+1
* ac/nir: implement half-float nir_op_frcpRhys Perry2019-02-191-2/+1
* ac/nir: make ac_build_fdiv support 16-bit floatsRhys Perry2019-02-191-1/+1
* ac/nir: make ac_build_isign work on all bit sizesRhys Perry2019-02-191-23/+4
* ac/nir: make ac_build_clamp work on all bit sizesRhys Perry2019-02-191-4/+9
* ac/nir: fix 64-bit nir_op_f2f16_rtzRhys Perry2019-02-191-0/+2
* ac/nir: implement 8-bit nir_load_const_instrRhys Perry2019-02-191-0/+4
* radv: ensure export arguments are always floatRhys Perry2019-02-191-5/+1
* radv: bitcast 16-bit outputs to integersRhys Perry2019-02-191-2/+2
* v3d: Move i2b and f2b support into emit_comparison.Eric Anholt2019-02-181-13/+12
* v3d: Emit a simpler negate for the iabs implementation.Eric Anholt2019-02-181-2/+1
* v3d: Delay emitting ldvpm on V3D 4.x until it's actually used.Eric Anholt2019-02-181-6/+43
* v3d: Stop tracking num_inputs for VPM loads.Eric Anholt2019-02-186-9/+4
* v3d: Add a function to describe what the c->execute.file check means.Eric Anholt2019-02-182-8/+14
* v3d: Fix the check for "is the last thrsw inside control flow"Eric Anholt2019-02-182-8/+17
* v3d: Fix f2b32 behavior.Eric Anholt2019-02-181-1/+6
* v3d: Kill off vir_PF(), which is hard to use right.Eric Anholt2019-02-183-70/+36
* v3d: Do bool-to-cond for discard_if as well.Eric Anholt2019-02-181-16/+12
* v3d: Refactor bcsel and if condition handling.Eric Anholt2019-02-181-29/+14
* v3d: Add a helper function for getting a nop register.Eric Anholt2019-02-185-14/+18
* v3d: Drop our hand-lowered nir_op_ffract.Eric Anholt2019-02-181-3/+1
* v3d: Drop a perf note about merging unpack_half_*, which has been implemented.Eric Anholt2019-02-181-3/+0
* v3d: Fix incorrect flagging of ldtmu as writing r4 on v3d 4.x.Eric Anholt2019-02-181-5/+4
* v3d: Use the early_fragment_tests flag for the shader's disable-EZ field.Eric Anholt2019-02-184-17/+23
* v3d: Sync indirect draws on the last rendering.Eric Anholt2019-02-181-2/+2
* v3d: Clear the GMP on initialization of the simulator.Eric Anholt2019-02-181-0/+1
* i965: always enable EXT_float_blendIlia Mirkin2019-02-181-0/+1
* st/mesa: enable GL_EXT_float_blend when possibleIlia Mirkin2019-02-181-0/+10
* mesa: add explicit enable for EXT_float_blend, and error conditionIlia Mirkin2019-02-184-1/+26
* radv: fix writing the alpha channel of MRT0 when alpha coverage is enabledSamuel Pitoiset2019-02-181-7/+8
* freedreno/ir3: handle quirky atomic dst for a6xxRob Clark2019-02-181-3/+12
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