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* nv50,nvc0: stop limiting the number of active queries to 1Samuel Pitoiset2016-11-022-16/+12
| | | | | | | | | | | | | | This limitation was initially here because AMD_performance_monitor doesn't allow to expose the real number of hardware counters. But this actually really annoying when profiling with qapitrace. Anyways, performance counters are mostly for developers and failures are expected if you try to monitor more queries than supported. This breaks amd_performance_monitor_measure but it's expected. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: add new warp_nonpred_execution_efficiency metric on SM35Samuel Pitoiset2016-11-022-1/+37
| | | | | | | Event not_predicated_off_thread_inst_executed is SM35+. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add missing metric-issue_slot on SM35Samuel Pitoiset2016-11-021-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: do not expose metric-inst_issued twice on SM35Samuel Pitoiset2016-11-021-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add new warp_execution_efficiency metric on SM30+Samuel Pitoiset2016-11-022-0/+24
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: respect 80-chars for perf metrics descriptionsSamuel Pitoiset2016-11-021-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: sort performance metrics alphabeticallySamuel Pitoiset2016-11-021-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radv: add support for anisotropic filtering on VI+Fredrik Höglund2016-11-031-3/+27
| | | | | | | Ported from radeonsi. Cc: "13.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: fix dual source blendingDave Airlie2016-11-031-3/+9
| | | | | | | | | | | Dolphin tried to use this, but we hadn't had any tests for it properly. All that is required is the shader output format needs to be set for 0 and 1 exports. Cc: "13.0" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50: add missing draw_calls_indexed driver statSamuel Pitoiset2016-11-021-0/+1
| | | | | | | Spotted when glancing at the VBO push code. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glx/glvnd: Use bsearch() in FindGLXFunction instead of open-coding itAdam Jackson2016-11-021-18/+16
| | | | | Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx/glvnd: Fix dispatch function names and indicesAdam Jackson2016-11-022-146/+144
| | | | | | | | | As this array was not actually sorted, FindGLXFunction's binary search would only sometimes work. Cc: "13.0" <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* glx/glvnd: Don't modify the dummy slot in the dispatch tableAdam Jackson2016-11-021-0/+3
| | | | | | Cc: "13.0" <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* anv/pipeline: Properly cache prog_data::paramJason Ekstrand2016-11-023-14/+36
| | | | | | | | | | | Before we were caching the prog data but we weren't doing anything with brw_stage_prog_data::param so anything with push constants wasn't getting cached properly. This commit fixes that. Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Timothy Arceri <[email protected]> Cc: "13.0" <[email protected]>
* anv/pipeline: Put actual pointers in anv_shader_binJason Ekstrand2016-11-025-50/+45
| | | | | | | | | | | | | | | While we can simply calculate offsets to get to things such as the prog_data and the key, it's much more user-friendly if there are just pointers. Also, it's a bit more fool-proof. While we're at it, we rework the pipeline cache API to use the brw_stage_prog_data type directly. Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: "13.0" <[email protected]>
* intel/blorp: Pass a brw_stage_prog_data to upload_shaderJason Ekstrand2016-11-025-6/+9
| | | | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: "13.0" <[email protected]>
* intel/blorp: Use wm_prog_data instead of hand-rolling our ownJason Ekstrand2016-11-025-66/+28
| | | | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98012 Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: "13.0" <[email protected]>
* anv: Better handle return codes from anv_physical_device_initJason Ekstrand2016-11-021-1/+1
| | | | | | | | | | | | The case where we just want the loop to continue is INCOMPATIBLE_DRIVER because that simply means that whatever FD we opened isn't a supported Intel chip. Other error codes such as OUT_OF_HOST_MEMORY are actual errors and we should be returning early in that case. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Cc: "13.0" <[email protected]>
* vulkan/wsi/x11: Clean up connections in finish_wsiJason Ekstrand2016-11-021-0/+4
| | | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Cc: "13.0" <[email protected]>
* vulkan/wsi/x11: Better handle wsi_x11_connection_create failureJason Ekstrand2016-11-021-0/+2
| | | | | | | | | | Without this fix, the function would still end up returning NULL but it would put that NULL connection in the hash table which would be bad. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Cc: "13.0" <[email protected]>
* glsl: compute lvalues of [in]out parameters before inlined function bodyNicolai Hähnle2016-11-021-10/+81
| | | | | | | | | | | | | | | This is required when an out argument involves an array index that is either a global variable modified by the function or another out argument in the same function call. Fixes the shaders/out-parameter-indexing/vs-inout-index-inout-* tests. v2: - modify the ir_dereference_array nodes in place - use ir_hierarchical_visitor v3: use base_ir (Ian Romanick) Reviewed-by: Ian Romanick <[email protected]>
* radeonsi: fix BFE/BFI lowering for GLSL semanticsNicolai Hähnle2016-11-021-3/+34
| | | | | | | Fixes spec/arb_gpu_shader5/execution/built-in-functions/*-bitfield{Extract,Insert} Cc: 13.0 <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: align the definition of BFI & [UI]BFE with GLSLNicolai Hähnle2016-11-021-20/+15
| | | | | | | | | | | | | | | As previously written, these opcodes use the SM5 semantics which is incompatible with GLSL when bits == 0, offset == 32. At some point we may want to add BFI_SM5 etc. opcodes, but all users currently either want (and expect!) the GLSL semantics or don't care. Bitfield inserts are generated by the GLSL lower_instructions and lower_packing_builtins passes with constant bits and offset arguments, so any workaround code that drivers may have to emit to follow GLSL semantics should be optimized away easily for those uses. Reviewed-by: Marek Olšák <[email protected]>
* radv: expose xlib platform extensionDave Airlie2016-11-021-0/+6
| | | | | | | | | I missed this when I added the xlib code, this allows dolphin emu to start and crash later. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "13.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* intel: aubinator: print field values if availableLionel Landwerlin2016-11-013-5/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turning this : sampler state 0 Sampler Disable: false Texture Border Color Mode: 0 LOD PreClamp Enable: 1 Base Mip Level: 0.000000 Mip Mode Filter: 0 Mag Mode Filter: 1 Min Mode Filter: 1 Texture LOD Bias: foo Anisotropic Algorithm: 0 into this : sampler state 0 Sampler Disable: false Texture Border Color Mode: 0 (DX10/OGL) LOD PreClamp Enable: 1 (OGL) Base Mip Level: 0.000000 Mip Mode Filter: 0 (NONE) Mag Mode Filter: 1 (LINEAR) Min Mode Filter: 1 (LINEAR) Texture LOD Bias: foo Anisotropic Algorithm: 0 (LEGACY) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Sirisha Gandikota<[email protected]>
* intel: aubinator: load fields values from xml dataLionel Landwerlin2016-11-012-0/+40
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Sirisha Gandikota<[email protected]>
* intel: aubinator: print boolean fields to true with colorsLionel Landwerlin2016-11-013-6/+17
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Sirisha Gandikota<[email protected]>
* amd: fix a typo in PIXEL_PIPE_STAT_RESET definitionMarek Olšák2016-11-011-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add enum radeon_micro_modeMarek Olšák2016-11-013-7/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: make it clear that DRM 2.x.x fast clear constraint is CIK-onlyMarek Olšák2016-11-011-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove r600_surface::level_infoMarek Olšák2016-11-013-7/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: add radeon_surf::is_linearMarek Olšák2016-11-018-13/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove radeon_surf_level::pitch_bytesMarek Olšák2016-11-0113-44/+48
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: don't call u_format helpers if we have that info alreadyMarek Olšák2016-11-012-10/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: replace radeon_surf_info::dcc_enabled with num_dcc_levelsMarek Olšák2016-11-016-15/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a driver query for counting CP DMA callsMarek Olšák2016-11-014-0/+13
| | | | | | | CP DMA calls are synchronous with regard to shaders, but can be made asynchronous if needed. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a driver query for shader cache hitsMarek Olšák2016-11-014-1/+16
| | | | | | This is an 8-month old patch. Reviewed-by: Nicolai Hähnle <[email protected]>
* gbm: set up the interop extension for egl/drmMarek Olšák2016-11-013-0/+3
| | | | | | | breaking libgbm -> libEGL ABI? Acked-by: Alex Deucher <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nvc0: do not duplicate similar performance metricsSamuel Pitoiset2016-11-011-43/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Pierre Moreau <[email protected]>
* anv/device: Return DEVICE_LOST if execbuf2 failsJason Ekstrand2016-11-011-6/+4
| | | | | | | | | | | This makes more sense than OUT_OF_HOST_MEMORY. Technically, you can recover from a failed execbuf2 but the batch you just submitted didn't fully execute so things are in an ill-defined state. The app doesn't want to continue from that point anyway. Signed-off-by: Jason Ekstrand <[email protected]> Cc: "13.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Fix vertex attrib upload for dvec3/4 shader inputsAntia Puentes2016-11-015-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The emission of vertex attributes corresponding to dvec3 and dvec4 vertex shader input variables was not correct when the <size> passed to the VertexAttribL* commands was <= 2. This was because we were using the vertex array size when emitting vertices to decide if we uploaded a 64-bit floating point attribute as 1 slot (128-bits) for sizes 1 and 2, or 2 slots (256-bits) for sizes 3 and 4. This caused problems when mapping the input variables to registers because, for deciding which registers contain the values uploaded for a certain variable, we use the size and type given to the variable in the shader, so we will be assigning 256-bits to dvec3/4 variables, even if we only uploaded 128-bits for them, which happened when the vertex array size was <= 2. The patch uses the shader information to only emit as 128-bits those 64-bit floating point variables that were declared as double or dvec2 in the vertex shader. Dvec3 and dvec4 variables will be always uploaded as 256-bits, independently of the <size> given to the VertexAttribL* command. From the ARB_vertex_attrib_64bit specification: "For the 64-bit double precision types listed in Table X.1, no default attribute values are provided if the values of the vertex attribute variable are specified with fewer components than required for the attribute variable. For example, the fourth component of a variable of type dvec4 will be undefined if specified using VertexAttribL3dv or using a vertex array specified with VertexAttribLPointer and a size of three." We are filling these unspecified components with zeros, which coincidentally is also what the GL44-CTS.vertex_attrib_binding.basic-inputL-case1 expects. v2: Do not use bitcount (Kenneth Graunke) Fixes: GL44-CTS.vertex_attrib_binding.basic-inputL-case1 test Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97287 Reviewed-by: Kenneth Graunke <[email protected]>
* radv: drop some unused cmask info members.Dave Airlie2016-11-012-8/+0
| | | | | | | | These were assigned but never used. Inspired by similiar patch in radeonsi. Signed-off-by: Dave Airlie <[email protected]>
* intel: aubinator: fix printing missing gen optionLionel Landwerlin2016-10-311-2/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: aubinator: fix assumptions on amount of required dataLionel Landwerlin2016-10-311-1/+5
| | | | | | | We require 12 bytes of headers but in some cases we just need 4. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel: aubinator: don't print out blocks twiceLionel Landwerlin2016-10-311-1/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Move gen8_disable_stages to brw_upload_initial_gpu_stateNanley Chery2016-10-314-56/+13
| | | | | | | | | | 3DSTATE_WM_CHROMAKEY isn't programmed anywhere else. 3DSTATE_WM_HZ_OP is programmed, then cleared by blorp during a HZ op, so repeatedly clearing it after every blorp execution is redundant. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_stateNanley Chery2016-10-313-36/+10
| | | | | | | This packet is non-pipelined and doesn't ever change across emissions. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/omx/dec: disable tunnel for size different caseLeo Liu2016-10-313-1/+11
| | | | | | | | | | When the video coded size is different from frame size, we need the result buffers are same as coded size, which are not size compatible with encode required size, so that simply use no tunnel for this case instead of frame by frame converting. Signed-off-by: Leo Liu <[email protected]> Cc: 13.0 <[email protected]>
* st/omx/dec: result buffers size should match codec decoder sizeLeo Liu2016-10-313-19/+18
| | | | | | | | Otherwise fails the check of matching between decoder size and buffers size in kernel. Signed-off-by: Leo Liu <[email protected]> Cc: 13.0 <[email protected]>
* swr: [rasterizer] added EventHandlerFile contructorGeorge Kyriazis2016-10-311-1/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
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