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* meson: build libEGLDylan Baker2017-10-206-25/+216
* meson: move wayland_drm_protocol generation to wayland-drmDylan Baker2017-10-202-15/+13
* nir: Print the components referenced for split or packed shader in/outs.Eric Anholt2017-10-201-1/+25
* nir: Add a safety check that we don't remove dead I/O vars after lowering.Eric Anholt2017-10-201-4/+14
* radv: disable implicit sync for radv allocated bos v3Andres Rodriguez2017-10-214-1/+8
* radv: factor out radv_alloc_memoryAndres Rodriguez2017-10-212-5/+25
* radv: Expose VK_EXT_global_priorityAndres Rodriguez2017-10-214-0/+5
* radv: don't skip PS/VS partial flushAndres Rodriguez2017-10-211-8/+6
* radv: Implement VK_EXT_global_priorityAndres Rodriguez2017-10-214-8/+62
* radeonsi: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez2017-10-211-7/+14
* radv: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez2017-10-211-9/+18
* vulkan: update headers & registry to VK 1.0.63Andres Rodriguez2017-10-211-84/+180
* broadcom/vc5: Use SETMSF to handle discards.Eric Anholt2017-10-202-25/+12
* broadcom/vc5: Set the snorm/unorm packing functions to be lowered.Eric Anholt2017-10-201-0/+4
* broadcom/vc5: Fix pasteo that broke vertex texturing.Eric Anholt2017-10-201-1/+1
* broadcom/vc5: Move default attribute value setup to the CSO and fix them.Eric Anholt2017-10-203-29/+23
* broadcom/vc5: Move most of the shader state attribute record to the CSO.Eric Anholt2017-10-204-65/+90
* broadcom/vc5: Fix build failure frm nir_shader::stage removal.Eric Anholt2017-10-201-4/+4
* i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner2017-10-201-4/+8
* i965: Add align1 ternary instruction emission supportMatt Turner2017-10-201-55/+160
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-202-75/+288
* i965: Add align1 ternary instruction-word supportMatt Turner2017-10-201-0/+108
* i965: Add align1 ternary instruction support to conversion functionsMatt Turner2017-10-204-34/+101
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-202-20/+23
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-203-18/+18
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-204-86/+92
* i965: Print subreg in units of type-size on ternary instructionsMatt Turner2017-10-201-5/+26
* i965: Add functions for brw_reg_type <-> hw 3src typeMatt Turner2017-10-202-0/+58
* i965: Move brw_reg_type_is_floating_point to brw_reg_type.hMatt Turner2017-10-202-13/+15
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-2050-187/+193
* radv: use optimal packet order for drawsSamuel Pitoiset2017-10-201-17/+79
* radv: add radv_emit_shaders_prefetch()Samuel Pitoiset2017-10-201-12/+19
* radv: add radv_emit_shader_prefetch()Samuel Pitoiset2017-10-201-25/+23
* st/mesa: correct a u_vbuf commentMarek Olšák2017-10-201-3/+5
* etnaviv: fix implicit conversion warningChristian Gmeiner2017-10-202-2/+2
* etnaviv: enable occlusion query if GPU supports itChristian Gmeiner2017-10-201-1/+2
* etnaviv: add support for occlusion queriesChristian Gmeiner2017-10-201-0/+78
* etnaviv: add basic infrastructure for hw queriesChristian Gmeiner2017-10-206-0/+292
* etnaviv: update headers from rnndbChristian Gmeiner2017-10-205-89/+622
* i965: Report supported context priorities to EGL/DRIChris Wilson2017-10-201-0/+13
* i965: Pass the EGL/DRI context priority through to the kernelChris Wilson2017-10-203-0/+46
* i965: Record the presence of the kernel schedulerChris Wilson2017-10-201-0/+11
* egl,dri: Propagate context priority hint to driver->CreateContextChris Wilson2017-10-2015-30/+71
* egl: Support IMG_context_priorityChris Wilson2017-10-205-0/+71
* radv: don't flush the VS when srcStageMask == TOP_OF_PIPE_BITFredrik Höglund2017-10-201-2/+1
* radv: mark total_count as MAYBE_UNUSED in CmdSet{Viewport,Scissor}Samuel Pitoiset2017-10-201-2/+2
* radv: rename radv_cmd_buffer_flush_state() to radv_draw()Samuel Pitoiset2017-10-201-59/+51
* radv: emit primitive restart from radv_emit_draw_registers()Samuel Pitoiset2017-10-201-29/+30
* radv: add radv_emit_draw_registers()Samuel Pitoiset2017-10-201-12/+34