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* loader: add dri_driver option to override dri driver to loadQiang Yu2018-08-172-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drirc implementation of MESA_LOADER_DRIVER_OVERRIDE which can be used to override dri driver to load. Usage: override dri driver for device with spec kernel driver name: <device kernel_driver="kernel_driver_name"> <option name="dri_driver" value="new_dri_driver" /> </device> or <device driver="loader" kernel_driver="kernel_driver_name"> <option name="dri_driver" value="new_dri_driver" /> </device> v2: add kernel_driver device attribute to specify kernel driver name instead of reuse driver attribute v3: seperate loader_get_kernel_driver_name into another patch seperate add kernel_driver attribute into another patch Suggested-by: Michel Dänzer <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]> [v4 Emil: add HAVE_LIBDRM guard around __driConfigOptionsLoader and loader_get_dri_config_driver] Signed-off-by: Emil Velikov <[email protected]>
* xmlconfig: add kernel_driver device attributeQiang Yu2018-08-1711-14/+23
| | | | | | | | | This attribute can be used by loader to apply different option to device use specific kernel driver. Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* loader: abstract loader_get_kernel_driver_name for reuseQiang Yu2018-08-171-16/+23
| | | | | | | | | This function can be shared by the following kernel_driver drirc patch. Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* driconf: move ${sysconfdir}/drirc to ${datadir}/drirc.d/00-mesa-defaults.confQiang Yu2018-08-173-3/+4
| | | | | | | | | ${sysconfdir} is for store admin config files, so move this mesa default config file to ${datadir}/drirc.d. Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* xmlconfig: read more config files from drirc.d/Qiang Yu2018-08-173-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | Driver and application can put their drirc files in ${datadir}/drirc.d/ with name xxx.conf. Config files will be read and applied in file name alphabetic order. So there are three places for drirc listed in order: 1. /usr/share/drirc.d/ 2. /etc/drirc 3. ~/.drirc v4: fix meson build v3: 1. seperate driParseConfigFiles refine into another patch 2. fix entries[i] mem leak v2: drop /etc/drirc.d Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* xmlconfig: refine driParseConfigFiles to use parseOneConfigFileEmil Velikov2018-08-171-34/+29
| | | | | | | | | | Also prepare for the usage of following parseConfigDir patch. Signed-off-by: Qiang Yu <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]> [Emil: add #include <limits.h>] Signed-off-by: Emil Velikov <[email protected]>
* anv/pipeline: Lower pipeline layouts etc. after linkingJason Ekstrand2018-08-171-30/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to use the link-optimized shader for determining binding table layouts and, more importantly, URB layouts. For apps running on DXVK, this is extremely important as DXVK likes to declare max-size inputs and outputs and this lets is massively shrink our URB space requirements. VkPipeline-db results (Batman pipelines only) on KBL: total instructions in shared programs: 820403 -> 790008 (-3.70%) instructions in affected programs: 273759 -> 243364 (-11.10%) helped: 622 HURT: 42 total spills in shared programs: 8449 -> 5212 (-38.31%) spills in affected programs: 3427 -> 190 (-94.46%) helped: 607 HURT: 2 total fills in shared programs: 11638 -> 6067 (-47.87%) fills in affected programs: 5879 -> 308 (-94.76%) helped: 606 HURT: 3 Looking at shaders by hand, it makes the URB between TCS and TES go from containing 32 per-vertex varyings per tessellation shader pair to a more reasonable 8-12. For a 3-vertex patch, that's at least half the URB space no matter how big the patch section is. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Set tess IO read/written key fields in compile_*Jason Ekstrand2018-08-171-9/+10
| | | | | | | | | We want these to be set as close to the final compile as possible so that they are guaranteed to happen after nir_shader_gather_info is called. The next commit is going to move nir_shader_gather_info to after the linking step which makes this necessary. Reviewed-by: Timothy Arceri <[email protected]>
* anv/pipeline: Use more fields from stage in compile_csJason Ekstrand2018-08-171-16/+21
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/apply_pipeline_layout: Add to the bind map instead of replacing itJason Ekstrand2018-08-173-59/+21
| | | | | | | | | | | This commit makes three changes. One is to only walk the descriptors once and set bind map sizes at the same time as filling out the entries. The second is to make the pass additive so that we can put stuff in the bind map before applying the pipeline layout. Third, we switch to using designated initializers. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/lower_ycbcr: Use the binding array size for bounds checksJason Ekstrand2018-08-171-6/+4
| | | | | | | | | | | Because lower_ycbcr gets called before apply_pipeline_layout, the indices are all logical and the binding layout HW size is actually too big for the bounds check. We should just use the regular logical array size instead. Fixes: f3e91e78a33 "anv: add nir lowering pass for ycbcr textures" Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* python: Open the template as text, with an explicit encodingMathieu Bridon2018-08-171-3/+2
| | | | | | | | | | | | | | | | | | | In commit bd27203f4d808763ac24ac94eb677cacf3e7cb99 we changed this to open in binary mode, to then explicitly decode the lines with the right encoding. Unfortunately, that broke the build on Windows, where the template file can have '\r\n' as line terminators: opening in binary mode would keep those terminators and break the regexp. We need to go back to text mode, where the "universal newlines" mode takes care of this. However, to fix the initial issue, let's specify the encoding explicitly when opening the file, and make sure it is open in text mode, so we only get unicode strings. Reviewed-by: Jose Fonseca <jfonseca@vmware>
* python: Help Python 2 print the lineMathieu Bridon2018-08-171-0/+5
| | | | Reviewed-by: Jose Fonseca <jfonseca@vmware>
* freedreno/a6xx: streamoutRob Clark2018-08-173-45/+62
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fragz fixesRob Clark2018-08-171-7/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: scissor fixesRob Clark2018-08-172-4/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-08-179-27/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix srgbRob Clark2018-08-171-7/+13
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix dEQP-GLES3.functional.fence_sync.*Rob Clark2018-08-171-0/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* radv/winsys: fix creating the BO list for virtual buffersSamuel Pitoiset2018-08-171-1/+1
| | | | | | | | | | | | | | When the number of unique BO is 0, we optimize the list creation by copying all buffers of the current CS directly into it. But this is only valid if the CS doesn't have virtual buffers, otherwise they are not added and hw might report VM faults. This fixes VM faults with: dEQP-VK.sparse_resources.image_sparse_binding.2d.rgba8ui.1024_128_1 CC: <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* freedreno: Add a6xx backendKristian H. Kristensen2018-08-1638-17/+6368
| | | | | | | | | | This adds a freedreno backend for the a6xx generation GPUs, which at the time of this commit is about 98% GLES2 conformant. Much remains to be done - both performance work and feature work towards more recent GLES versions, but this is a good start. Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-08-167-66/+4928
| | | | | | pull in a6xx registers Signed-off-by: Rob Clark <[email protected]>
* freedreno: Fix warningsKristian H. Kristensen2018-08-165-15/+9
| | | | | Signed-off-by: Kristian H. Kristensen <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* svga: simplify Mesa version stringEric Engestrom2018-08-161-1/+1
| | | | | | Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* bin: always define MESA_GIT_SHA1 to make it directly usable in codeEric Engestrom2018-08-165-25/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* git_sha1: simplify logicEric Engestrom2018-08-163-3/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused assignmentEric Engestrom2018-08-161-2/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: drop cast-to-void of used variableEric Engestrom2018-08-161-1/+0
| | | | | | | `device` is used 2 lines below, even visible in the diff context printed. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: use safer snprintf() to ensure NULL string-terminatorEric Engestrom2018-08-161-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()Eric Engestrom2018-08-161-3/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: various python cleanupsEric Engestrom2018-08-165-26/+21
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl: check for buffer overflow *before* corrupting our memoryEric Engestrom2018-08-161-4/+15
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl/wayland: remove sign from bitfield `formats`Eric Engestrom2018-08-162-6/+6
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* egl: some spelling fixesEric Engestrom2018-08-161-5/+5
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* radv: initialize the DCC predicate correctly when it's compressedSamuel Pitoiset2018-08-161-1/+4
| | | | | | | | | | We have to do a fast-clear eliminate when clearing DCC metadata with 0x20202020. I don't know if that fixes anything but that seems correct to me. CC: 18.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix missing initialization of the conditional rendering stateSamuel Pitoiset2018-08-161-0/+1
| | | | | | | | | | | | | | This was missing when VK_EXT_conditional_rendering has been implemented. The predication type should be -1 to avoid restoring previous state when performing a decompression pass with DCC enabled. Note that we don't have to handle secondary command buffers because we don't support this feature currently. CC: 18.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Revert divisor = 0 case for vertex attribute extension.Bas Nieuwenhuizen2018-08-161-1/+1
| | | | | | | | | | Seems like DXVK depends on that and it might get reverted upstream. Since apps are not supposed to use 0 in v2 anyway, we should be safe implementing the old behavior there. Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 2." CC: 18.2 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Possible on-demand compilation fix.Bas Nieuwenhuizen2018-08-161-0/+8
| | | | | | | | | | Seems that in a single case we use the renderpass before checking the pipeline, so check the renderpass before we use it. Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders." Tested-by: Timothy Arceri <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa/st: fix array indices off-by-one error in remappingGert Wollny2018-08-162-6/+6
| | | | | | | | | | | | | | | When moving the array sizes from the old list to the new one it was not taken into account that the array indices start with one, but the array_size array started at index zero, which resulted in incorrect array sizes when arrays were merged. Correct this by copying the array_size values of the retained arrays with an offset of -1. Also fix whitespaces for the replaced lines. Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e mesa/st/glsl_to_tgsi: Expose array live range tracking and merging Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* meson: fix build for egl platform_x11 without dri3 and gbmAlexander Tsoy2018-08-151-1/+1
| | | | | | | | | | | | | | | | Compiling EGL's platform_x11 without dri3 and gbm yields this compile failure: platform_x11 needs inc_loader: ../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal error: loader.h: No such file or directory #include "loader.h" ^~~~~~~~~~ Fixes: 108d257a1685 ("meson: build libEGL") Bugzilla: https://bugs.gentoo.org/663534 Reviewed-by: Matt Turner <[email protected]>
* Revert "intel/nir: Call nir_lower_io_to_scalar_early"Jason Ekstrand2018-08-151-12/+5
| | | | | | | | | | | | | Commit 4434591bf56a6b0 caused substantially more URB messages in geometry and tessellation shaders. Before we can really enable this sort of optimization, We either need some way of combining them back together into vectors or we need to do cross-stage vector element elimination without splitting everything into scalars. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510 Fixes: 4434591bf56a6 "intel/nir: Call nir_lower_io_to_scalar_early" Acked-by: Kenneth Graunke <[email protected]> Tested-by: Mark Janes <[email protected]>
* i965: do not emit empty surface stateErik Faye-Lund2018-08-151-0/+5
| | | | | | | | | | | | | | If called with an empty size, brw_emit_buffer_surface_state asserts. We already have a dedicated helper for uploading nothing, so let's use that instead. Avoids an assert in dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex when running a debug build of i965. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/ppgtt: 4096 replaced by PAGE_SIZESergii Romantsov2018-08-151-6/+6
| | | | | | | Usage of number 4096 replaced by PAGE_SIZE. Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/ppgtt: memory address alignmentSergii Romantsov2018-08-151-4/+3
| | | | | | | | | | | | | | | | | | Kernel (for ppgtt) requires memory address to be aligned to page size (4096). -v2: added marking that also fixes initial commit 01058a552294. -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned instead of alignment of offsets (Chris Wilson). -v4: changes related to PAGE_SIZE moved to separate commit -v5: restored alignment to page-size for 0-size. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997 Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.) Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.) Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: add Doom workaroundTimothy Arceri2018-08-161-0/+3
| | | | | | Cc: <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Emitting 3DSTATE_SO_BUFFER of 0-size.Sergii Romantsov2018-08-151-4/+5
| | | | | | | Avoided filling of whole structure and bo-allocation if size of surface is 0. Signed-off-by: Sergii Romantsov <[email protected]>
* virgl: report actual max-texture sizesErik Faye-Lund2018-08-152-0/+10
| | | | | | | | Instead of doing conservative guesses, we should report the max levels based on the max sizes we get from GL on the host. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* virgl: do not use SP_MAX_TEXTURE_*_LEVELS definesErik Faye-Lund2018-08-151-7/+3
| | | | | | | | | | | | | These macro-names are also used for softpipe, so let's avoid confusion by avoiding them. Besides, they are just used in one place in virgl, so let's just inline them into the place they are used instead. While we're at it, fixup an error in the comment for the 3D version. Mesa subtracts computes max-size by doing by 2^(n-1), which means this should be 256 cubed, not 512 cubed. The other comments are correct. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* radv: disable the auto-waitcnt-before-barrier LLVM optionSamuel Pitoiset2018-08-153-1/+4
| | | | | | | | | | | | | | This option allows us to remove additional s_waitcnt instructions because s_barrier internally does s_waitcnt 0. Though, apparently there is a problem with LDS accesses that causes rendering issues with FFXV and DXVK. Disable this optimization for now (RadeonSI still uses it). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460 CC: 18.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix memory leaks in radv_load_meta_pipeline()Samuel Pitoiset2018-08-151-2/+3
| | | | | | | | Reported by Coverity. Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
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