Commit message (Collapse) | Author | Age | Files | Lines | |
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* | radeonsi: don't load unused compute shader input SGPRs and VGPRs | Marek Olšák | 2017-04-28 | 4 | -48/+76 |
| | | | | | | | | | Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine whether to load BLOCK_ID for each component separately, and set the number of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave rate in most cases. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | tgsi/scan: record compute shader system value usage | Marek Olšák | 2017-04-28 | 2 | -0/+37 |
| | | | | | | v2: just do indexing with swizzle[i] Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: add a HUD query for draw calls with primitive restart | Marek Olšák | 2017-04-28 | 4 | -0/+11 |
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> | ||||
* | radeonsi: tell LLVM not to remove s_barrier instructions | Marek Olšák | 2017-04-28 | 1 | -12/+33 |
| | | | | | | | LLVM 5.0 removes s_barrier instructions if the max-work-group-size attribute is not set. What a surprise. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: fix tess offchip offset for per-patch attributes | Marek Olšák | 2017-04-28 | 3 | -12/+18 |
| | | | | | | We need 4 more bits there. I don't know what is fixed by this. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: pass tessellation ring addresses via user SGPRs | Marek Olšák | 2017-04-28 | 7 | -56/+112 |
| | | | | | | | | | | | | | | | | | This removes s_load_dword latency for tess rings. We need just 1 SGPR for the address if we use 64K alignment. The final asm for recreating the descriptor is: // s2 is (address >> 16) s_mov_b32 s3, 0 s_lshl_b64 s[4:5], s[2:3], 16 s_mov_b32 s6, -1 s_mov_b32 s7, 0x27fac v2: bitcast the descriptor type from v2i64 to v4i32 Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue | Marek Olšák | 2017-04-28 | 1 | -19/+10 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: remove VS epilog code, compile VS with PrimID export on demand | Marek Olšák | 2017-04-28 | 5 | -210/+31 |
| | | | | | | | | | | | | The use of PrimID in the pixel shader is too rare to deserve such a sizable support code. The initial idea of the VS epilog was to move the clipping code there and remove it based on states, but optimized variants are now used to do that and are easier to support, so the VS epilog has turned out to be not so useful. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3 | Marek Olšák | 2017-04-28 | 4 | -13/+33 |
| | | | | | | VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1 Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: don't load PrimID in TES if it's not used | Marek Olšák | 2017-04-28 | 1 | -3/+3 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: explain (non-)monolithic shaders | Marek Olšák | 2017-04-28 | 1 | -0/+67 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: enable OpenGL 4.5 | Marek Olšák | 2017-04-28 | 1 | -5/+0 |
| | | | | | | | Tentatively enable it, expecting the scratch buffer support to be done before the next Mesa release. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st | Marek Olšák | 2017-04-28 | 2 | -10/+26 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: add reference counting for shader selectors | Marek Olšák | 2017-04-28 | 2 | -3/+25 |
| | | | | | | | The 2nd shader of merged shaders should take a reference of the 1st shader. The next commit will do that. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS | Marek Olšák | 2017-04-28 | 1 | -6/+12 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set TES registers for merged ES-GS | Marek Olšák | 2017-04-28 | 1 | -4/+7 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS | Marek Olšák | 2017-04-28 | 1 | -0/+10 |
| | | | | | | not implemented yet Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: always compile monolithic ES-GS (asynchronously) | Marek Olšák | 2017-04-28 | 2 | -1/+28 |
| | | | | | | In addition to the non-monolithic variant. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add support for monolithic ES-GS | Marek Olšák | 2017-04-28 | 2 | -9/+72 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders | Marek Olšák | 2017-04-28 | 1 | -18/+60 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: select shader parts for non-monolithic ES-GS | Marek Olšák | 2017-04-28 | 1 | -3/+14 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add GS prolog support for merged ES-GS | Marek Olšák | 2017-04-28 | 1 | -17/+70 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add VS prolog support for merged ES-GS | Marek Olšák | 2017-04-28 | 1 | -0/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS | Marek Olšák | 2017-04-28 | 1 | -0/+32 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: store ES outputs to LDS | Marek Olšák | 2017-04-28 | 1 | -4/+17 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: load GS inputs from LDS | Marek Olšák | 2017-04-28 | 1 | -6/+39 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: get GS wave ID from the correct input | Marek Olšák | 2017-04-28 | 1 | -3/+11 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add the function signature of merged ES-GS | Marek Olšák | 2017-04-28 | 2 | -12/+74 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set registers and shader key for merged ES-GS | Marek Olšák | 2017-04-28 | 5 | -27/+218 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add GS user SGPRs | Marek Olšák | 2017-04-28 | 4 | -7/+25 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: rename declare_tess_lds -> declare_lds_as_pointer | Marek Olšák | 2017-04-28 | 1 | -4/+4 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: simplify some shader type conditions | Marek Olšák | 2017-04-28 | 1 | -6/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: rename the swizzle parameter of lds_store | Marek Olšák | 2017-04-28 | 1 | -2/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: add si_shader::prolog2 | Marek Olšák | 2017-04-28 | 3 | -1/+25 |
| | | | | | | For a GS prolog in merged ES-GS. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders | Marek Olšák | 2017-04-28 | 3 | -21/+24 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add support for monolithic merged LS-HS | Marek Olšák | 2017-04-28 | 2 | -17/+128 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them | Marek Olšák | 2017-04-28 | 1 | -2/+41 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: don't store the HS control word | Marek Olšák | 2017-04-28 | 1 | -7/+12 |
| | | | | | | GFX9 doesn't have it. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: pass inputs from LS to TCS | Marek Olšák | 2017-04-28 | 2 | -2/+69 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add TCS epilog support for merged LS-HS | Marek Olšák | 2017-04-28 | 1 | -34/+76 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add VS prolog support for merged LS-HS | Marek Olšák | 2017-04-28 | 2 | -10/+21 |
| | | | | | | HS input VGPRs must be reserved. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: merged shaders have scratch offset at the beginning | Marek Olšák | 2017-04-28 | 2 | -1/+13 |
| | | | | | | also, screen wasn't initialized for compute shaders Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: define LS-HS main shader function prototype | Marek Olšák | 2017-04-28 | 1 | -38/+147 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamically | Marek Olšák | 2017-04-28 | 3 | -193/+190 |
| | | | | | | They will vary with merged stages. Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: define and set LS-HS user SGPRs | Marek Olšák | 2017-04-28 | 5 | -20/+57 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: set up shader registers for merged LS-HS | Marek Olšák | 2017-04-28 | 3 | -15/+55 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add initial code generation for non-monolithic merged LS-HS | Marek Olšák | 2017-04-28 | 3 | -1/+23 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi: separate out code for selecting the VS prolog | Marek Olšák | 2017-04-28 | 1 | -17/+29 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: add si_shader::previous_stage for merged shaders | Marek Olšák | 2017-04-28 | 3 | -1/+39 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> | ||||
* | radeonsi/gfx9: enlarge num_input_sgprs in shader keys due to higher hw limit | Marek Olšák | 2017-04-28 | 1 | -2/+2 |
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> |