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* i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
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* i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
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* i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
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* i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
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* i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
| | | | | This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
* i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
| | | | | | | | This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
* st/xorg: implement batching for the composite opZack Rusin2009-11-064-90/+161
| | | | something is broken so disabled for now
* st/xorg: batch solid fill requestsZack Rusin2009-11-064-95/+66
| | | | | instead of lots of very small transfers, one larger is a lot better for performance
* st/xorg: start accumulating vertices in a common bufferZack Rusin2009-11-062-48/+88
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* st/xorg: use quads instead of triangle fansZack Rusin2009-11-061-4/+4
| | | | easier to split, accumulate and batch those
* st/xorg: make the buffer size globalZack Rusin2009-11-061-1/+9
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* mesa: Reduce the source channels considered in optimization passes.Eric Anholt2009-11-061-1/+40
| | | | | | | Depending on the writemask or the opcode, we can often trim the source channels considered used for dead code elimination. This saves actual instructions on 965 in the non-GLSL path for glean glsl1, and cleans up the writemasks of programs even further.
* mesa: Fix remove_instructions to successfully remove when removeFlags[0].Eric Anholt2009-11-061-0/+6
| | | | | This fixes the dead code elimination to work on the particular code mentioned in the previous commit.
* mesa: Add an optimization path to remove use of pointless MOVs.Eric Anholt2009-11-061-1/+83
| | | | | | | | | | | | | | | | | | GLSL code such as: vec4 result = {0, 1, 0, 0}; gl_FragColor = result; emits code like: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], TEMP[0]; and this replaces it with: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], CONST[0]; Even when the dead code eliminator fails to clean up a now-useless MOV instruction (since it doesn't do live/dead ranges), this should at reduce dependencies.
* mesa: Fix up the remove_dead_code pass to operate on a channel basis.Eric Anholt2009-11-061-28/+56
| | | | | | | This cleans up a bunch of instructions in GLSL programs to have limited writemasks, which would translate to wins in shaders that hit the i965 brw_wm_glsl.c path by depending less on in-driver optimizations. It will also help hit other optimization passes I'm looking at.
* intel: better front color buffer test in intelClear()Brian Paul2009-11-061-2/+3
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* i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
| | | | | This keeps the individual state files from having to export their structures for brw_state_cache initialization.
* intel: Finish removing the fallback code for bug #16697.Eric Anholt2009-11-061-6/+2
| | | | I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
* intel: Don't validate in a texture image used as a render target.Eric Anholt2009-11-063-11/+15
| | | | | Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation.
* mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture()Eric Anholt2009-11-061-0/+4
| | | | | | | | | | This is probably not 100% complete (bind vs unbind may still not pair up exactly), but it should help out drivers which are relying on FinishRenderTexture to be called when we're done rendering to a particular texture level, not just when we're done rendering to the object at all. This is the case for the one consumer of FinishRenderTexture() so far: the gallium state tracker. Noticed when trying to make use of FRT() in the intel driver.
* intel: Clean up some extra struct indirection in finalize.Eric Anholt2009-11-061-2/+1
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* intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt2009-11-061-4/+4
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* intel: Remove duplicated arguments from intel_miptree_match_image().Eric Anholt2009-11-063-10/+7
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* i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt2009-11-061-1/+0
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* intel: Remove obsolete comment about GEM in the spans code.Eric Anholt2009-11-061-1/+0
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* intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt2009-11-067-51/+37
| | | | | | This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
* Make a convenient int for what chipset generation we're on.Eric Anholt2009-11-065-9/+20
| | | | | | gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks.
* Merge branch 'mesa_7_6_branch'Ian Romanick2009-11-068-570/+508
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should fix the memory leaks in the assembly parser without the regressions. The conflicts in program_lexer.l were related to changes in returning strings between the branches (always return IDENTIFIER vs. returing either IDENTIFIER or USED_IDENTIFIER). The conflicts in program_parse.y were related to two changes in master One change prints a variable name in an error message. The other change adds outputVarSize to the OUTPUT_statement rule. The cause the position of the IDENTIFIER to change from $2 to $3. Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_lexer.l src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.y
| * ARB prog parser: Regenerate parser from previous commits.Ian Romanick2009-11-061-242/+268
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| * ARB prog parser: Release old program string in ↵Ian Romanick2009-11-062-4/+6
| | | | | | | | | | | | | | | | | | _mesa_parse_arb_{fragment,vertex}_program The program structure passed to _mesa_parse_arb_program is just a place holder. The stings that actually need to be released are only known to the functions calling _mesa_parse_arb_program, so they should be freed there.
| * ARB prog parser: Release strings returned from the lexer that don't need to ↵Ian Romanick2009-11-061-1/+27
| | | | | | | | be kept
| * Revert "ARB prog parser: Fix epic memory leak in lexer / parser interface"Ian Romanick2009-11-065-337/+207
| | | | | | | | | | | | | | | | This reverts commit 93dae6761bc90bbd43b450d2673620ec189b2c7a. This change was completely broken when the parser uses multiple strings in a single production. It would be nice if bug fixes could initially land somewhere other than the stable branch.
| * xmesa: pass pixmap to clip_for_xgetimage()Brian Paul2009-11-051-4/+4
| | | | | | | | | | | | The code was assuming ctx->DrawBuffer == ctx->ReadBuffer. Passing the pixmap is simpler and better. Fixes a potential segfault.
| * mesa: added cast to silence warningBrian Paul2009-11-041-1/+1
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* | llvmpipe: Fix build with llvm 2.6.José Fonseca2009-11-062-5/+10
| | | | | | | | Fixes bug 24949.
* | intel: call intel_check_front_buffer_rendering() in intelClear()Brian Paul2009-11-061-0/+3
| | | | | | | | fixes bug 24953.
* | mesa: Export S3_s3tc as well.José Fonseca2009-11-061-0/+1
| | | | | | | | Used in Quake3.
* | mesa: Translate MAP_UNSYNCHRONIZED_BIT.José Fonseca2009-11-061-0/+3
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* | gallium: Add UNSYNCHRONIZED cpu access flag. Document others.José Fonseca2009-11-061-2/+57
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* | st/xorg: unify vertex buffer handlingZack Rusin2009-11-062-68/+66
| | | | | | | | first step on our way to batching
* | mesa: fix infinite loop bug in _mesa_drawbuffers()Brian Paul2009-11-051-1/+2
| | | | | | | | | | Fixes bug 24946. This regression came from 8df699b3bb1aa05b633f05b121d09d812c86a22d.
* | softpipe: Implement PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE for destination.José Fonseca2009-11-051-2/+10
| | | | | | | | It is a valid and tested combination on D3D9.
* | g3dvl: remove a debug lineCooper Yuan2009-11-051-1/+0
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* | g3dvl: add scissor settingCooper Yuan2009-11-054-0/+13
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* | r300g: add polygon modeMarek Olšák2009-11-045-3/+67
| | | | | | | | Signed-off-by: Corbin Simpson <[email protected]>
* | r300g: fix the size of CS when emitting the fragprog constant bufferMarek Olšák2009-11-041-1/+1
| | | | | | | | Signed-off-by: Corbin Simpson <[email protected]>
* | r300g: set the correct offset in a colorbuffer surfaceMarek Olšák2009-11-041-8/+9
| | | | | | | | | | | | | | | | | | Suggested by Joakim Sindholt. Also, put flushing of colorbuffers _before_ the framebuffer state setup, suggested by docs. Signed-off-by: Corbin Simpson <[email protected]>
* | r300g: add color channel maskingMarek Olšák2009-11-044-5/+19
| | | | | | | | Signed-off-by: Corbin Simpson <[email protected]>
* | Merge branch 'mesa_7_6_branch'Brian Paul2009-11-049-191/+191
|\| | | | | | | | | | | Conflicts: src/mesa/drivers/windows/gdi/mesa.def
| * vbo: fix out-of-bounds array accessBrian Paul2009-11-043-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | The exec->vtx.inputs[] array was being written past its end. This was clobbering the following vbo_exec_context::eval state. Probably not noticed since evaluators and immediate mode rendering don't happen at the same time. Fixed the loop in vbo_exec_vtx_init(). Changed the size of the vbo_exec_context::vtx.arrays[] array. Added a bunch of debug-build assertions. Issue found by Vinson Lee.
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