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* Use calloc instead of malloc/memset-0Matt Turner2014-12-081-2/+1
* Remove useless checks for NULL before freeingMatt Turner2014-12-0820-72/+39
* i965/skl: Add Skylake PCI IDsKristian Høgsberg2014-12-081-0/+29
* i965/skl: Emit depth stall workaround for gen9 as wellDamien Lespiau2014-12-081-1/+1
* i965/skl: Fix GS thread count locationBen Widawsky2014-12-081-11/+18
* i965: Fix union usage for G++ <= 4.6.Vinson Lee2014-12-081-1/+2
* vc4: Interleave register allocation from regfile A and B.Eric Anholt2014-12-081-39/+38
* vc4: Fix decision for whether the MIN operation writes to the B regfile.Eric Anholt2014-12-081-3/+3
* vc4: Drop dependency on r3 for color packing.Eric Anholt2014-12-081-4/+27
* vc4: Add support for GL 1.0 logic ops.Eric Anholt2014-12-081-2/+60
* vc4: Add support for TGSI_OPCODE_UCMP.Eric Anholt2014-12-081-0/+12
* radeonsi/compute: Clamp COMPUTE_TMPRING_SIZE.WAVES to: num_cu * 32Tom Stellard2014-12-081-0/+3
* winsys/radeon: Always report at least 1 compute unitTom Stellard2014-12-082-1/+3
* radeonsi: Program RASTER_CONFIG for harvested GPUs v5Tom Stellard2014-12-084-6/+134
* draw: (trivial): remove double semicolonRoland Scheidegger2014-12-091-1/+1
* st/mesa: For vertex shaders, don't emit saturate when SM 3.0 is unsupportedAbdiel Janulgue2014-12-082-4/+3
* glsl: Don't optimize min/max into saturate when EmitNoSat is setAbdiel Janulgue2014-12-082-1/+2
* ir_to_mesa: Remove sat to clamp lowering passAbdiel Janulgue2014-12-081-3/+1
* loader: Add missing EXPAT_CFLAGS to libloader.la CPPFLAGSMichael Forney2014-12-081-1/+2
* i965: Remove default from brw_instruction_name switch to catch missing names.Matt Turner2014-12-081-12/+5
* i965: Add missing opcode names.Matt Turner2014-12-081-0/+9
* i965: Add opcode names for set_omask and set_sample_id.Matt Turner2014-12-081-0/+4
* egl: Expose EGL_KHR_get_all_proc_addresses and its client extensionChad Versace2014-12-075-1/+23
* freedreno/a2xx: silence warning about missing DEPTH32XIlia Mirkin2014-12-061-1/+4
* freedreno/a3xx: handle index_bias (i.e. base_vertex)Ilia Mirkin2014-12-061-3/+13
* freedreno/a3xx: add bgr565 texturing and renderingIlia Mirkin2014-12-061-1/+1
* freedreno/a3xx: add support for SRGB render targetsIlia Mirkin2014-12-062-9/+12
* freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputsIlia Mirkin2014-12-063-1/+17
* freedreno/a3xx: re-enable rgb10_a2 render targetsIlia Mirkin2014-12-061-1/+3
* freedreno/a3xx: fix border color swizzle to match texture format descIlia Mirkin2014-12-061-4/+18
* freedreno/a3xx: fix alpha-blending on RGBX formatsIlia Mirkin2014-12-065-8/+55
* glcpp: Fix `can not` to `cannot` in error messageChris Forbes2014-12-072-4/+4
* glcpp: Disallow undefining GL_* builtin macros.Chris Forbes2014-12-071-1/+2
* i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)Chris Forbes2014-12-071-0/+6
* i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSETChris Forbes2014-12-071-0/+2
* i965: Add opcode names for FS interpolation opcodesChris Forbes2014-12-071-0/+9
* mesa/st: don't use CMP / I2F for conditional assignments with native integersRoland Scheidegger2014-12-061-17/+45
* llvmpipe: decrease MAX_SCENES from 2 to 1Roland Scheidegger2014-12-062-1/+13
* draw: use the prim type from prim_info not emit in passthrough emitRoland Scheidegger2014-12-061-2/+2
* draw: use correct output prim for non-adjacent topologies in prim assembler.Roland Scheidegger2014-12-061-4/+4
* draw: kill off unneded prim assembler code for handling adjacency vertsRoland Scheidegger2014-12-062-60/+0
* gallium/docs: (trivial) remove STR opcode description.Roland Scheidegger2014-12-061-9/+0
* i965/fs: Perform CSE on MOV ..., VF instructions.Matt Turner2014-12-051-5/+11
* i965/fs: Try to emit LINE instructions on Gen <= 5.Matt Turner2014-12-052-0/+56
* i965/fs: Add support for generating the LINE instruction.Matt Turner2014-12-051-0/+4
* i965: Set the region of LINE's src0 to <0,1,0>.Matt Turner2014-12-051-1/+10
* i965: Give compile stats through KHR_debug.Matt Turner2014-12-052-0/+20
* mesa: Add a source parameter to _mesa_gl_debug.Matt Turner2014-12-057-2/+12
* vc4: Try swapping the regfile A to B to pair instructions.Eric Anholt2014-12-051-2/+62
* vc4: Allow pairing of some instructions that disagree about the WS bit.Eric Anholt2014-12-051-1/+47
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