| Commit message (Expand) | Author | Age | Files | Lines |
* | st/mesa: quick fix of CopyPixels with GL_DEPTH_STENCIL | Marek Olšák | 2011-11-22 | 1 | -0/+7 |
* | linker: Remove erroneous multiply by 4 in uniform usage calculation | Ian Romanick | 2011-11-22 | 1 | -5/+5 |
* | Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesa | Chad Versace | 2011-11-22 | 42 | -792/+2130 |
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| * | i965/gen6: Enable HiZ by default | Chad Versace | 2011-11-22 | 1 | -6/+2 |
| * | intel: Use separate stencil whenever possible | Chad Versace | 2011-11-22 | 2 | -2/+2 |
| * | i965: Implement the actual tables for texture alignment units [v2] | Kenneth Graunke | 2011-11-22 | 3 | -13/+105 |
| * | i965/gen6: Set vertical alignment in SURFACE_STATE batch | Chad Versace | 2011-11-22 | 2 | -6/+11 |
| * | intel: Store miptree alignment units in the miptree | Chad Versace | 2011-11-22 | 4 | -32/+26 |
| * | intel: Enable HiZ for texture renderbuffers | Chad Versace | 2011-11-22 | 1 | -0/+7 |
| * | intel: Resolve buffers in intel_map_renderbuffer() | Chad Versace | 2011-11-22 | 1 | -0/+5 |
| * | intel: Resolve buffers in intel_map_texture_image() | Chad Versace | 2011-11-22 | 1 | -0/+5 |
| * | intel: Mark needed resolves when first enabling HiZ on a miptree | Chad Versace | 2011-11-22 | 1 | -1/+20 |
| * | i965: Mark that depth buffer needs depth resolve after drawing | Chad Versace | 2011-11-22 | 1 | -0/+23 |
| * | intel: Resolve buffers in intelSpanRenderStart | Chad Versace | 2011-11-22 | 1 | -1/+39 |
| * | intel: Refactor intelSpanRenderStart | Chad Versace | 2011-11-22 | 1 | -16/+25 |
| * | i965: Resolve buffers before drawing [v2] | Chad Versace | 2011-11-22 | 1 | -0/+73 |
| * | i965: Prevent recursive calls to FLUSH_VERTICES [v2] | Chad Versace | 2011-11-22 | 1 | -0/+66 |
| * | i965/gen6: Manipulate state batches for HiZ meta-ops [v4] | Chad Versace | 2011-11-22 | 8 | -9/+74 |
| * | i965/gen6: Complete stubs for HiZ buffer resolves | Chad Versace | 2011-11-22 | 1 | -2/+298 |
| * | i965: Add HiZ operation state to brw_context | Chad Versace | 2011-11-22 | 1 | -0/+35 |
| * | intel: Add resolve functions for renderbuffers | Chad Versace | 2011-11-22 | 2 | -0/+94 |
| * | intel: Add resolve functions for miptrees | Chad Versace | 2011-11-22 | 2 | -1/+174 |
| * | intel: Add field intel_mipmap_tree::hiz_map | Chad Versace | 2011-11-22 | 1 | -0/+13 |
| * | intel: Define struct intel_resolve_map [v2] | Chad Versace | 2011-11-22 | 4 | -0/+196 |
| * | intel: Change signature of HiZ resolve functions | Chad Versace | 2011-11-22 | 4 | -19/+32 |
| * | intel: Remove unused HiZ functions | Chad Versace | 2011-11-22 | 3 | -27/+0 |
| * | intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2] | Chad Versace | 2011-11-22 | 5 | -30/+50 |
| * | intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stenc... | Chad Versace | 2011-11-22 | 6 | -236/+252 |
| * | intel: Refactor intel_render_texture() [v2] | Chad Versace | 2011-11-22 | 1 | -33/+88 |
| * | intel: Define intel_miptree_check_level_layer() | Chad Versace | 2011-11-22 | 1 | -0/+13 |
| * | intel: Remove unneeded params from intel_renderbuffer_set_draw_offset() | Chad Versace | 2011-11-22 | 3 | -14/+10 |
| * | intel: Track the miptree layer wrapped by a renderbuffer [v2] | Chad Versace | 2011-11-22 | 2 | -5/+49 |
| * | intel: Kill intel_mipmap_level::nr_images [v4] | Chad Versace | 2011-11-22 | 6 | -43/+57 |
| * | intel: Refactor intel_miptree_copy_teximage() | Chad Versace | 2011-11-21 | 1 | -56/+66 |
| * | intel: Refactor intel_mipmap_level offsets | Chad Versace | 2011-11-21 | 2 | -25/+37 |
| * | intel: Replace intel_renderbuffer::region with a miptree [v3] | Chad Versace | 2011-11-21 | 16 | -140/+203 |
| * | intel: Define intel_miptree_create_for_renderbuffer() | Chad Versace | 2011-11-21 | 2 | -0/+36 |
| * | intel: Move inline functions from intel_fbo.h to .c | Chad Versace | 2011-11-21 | 2 | -17/+23 |
| * | intel: Kill intel_framebuffer_get_hiz_region() | Chad Versace | 2011-11-21 | 1 | -17/+3 |
| * | intel: Temporarily disable HiZ for textures | Chad Versace | 2011-11-21 | 1 | -59/+3 |
| * | intel: Always gather stencil buffer in intel_map_renderbuffer_separate_s8z24() | Chad Versace | 2011-11-21 | 1 | -32/+20 |
| * | intel: Fix swrast_render_start() for depthstencil buffers with separate stencil | Chad Versace | 2011-11-21 | 2 | -29/+15 |
| * | intel: Don't use special stencil span accessors | Chad Versace | 2011-11-21 | 1 | -42/+1 |
| * | nvc0: add support for GF119 (NVD9) | Ben Skeggs | 2011-11-18 | 2 | -0/+2 |
* | | i915g: implement RGBX and BGRX render targets | Vasily Khoruzhick | 2011-11-22 | 2 | -2/+7 |
* | | st/mesa: fix accum buffer allocation in st_renderbuffer_alloc_storage() | Brian Paul | 2011-11-22 | 1 | -2/+12 |
* | | r600g: handle PIPE_SHADER_CAP_OUTPUT_READ | Vadim Girlin | 2011-11-21 | 1 | -0/+2 |
* | | st/mesa: use PIPE_SHADER_CAP_OUTPUT_READ | Vadim Girlin | 2011-11-21 | 1 | -4/+12 |
* | | gallium: add PIPE_SHADER_CAP_OUTPUT_READ | Vadim Girlin | 2011-11-21 | 2 | -2/+2 |
* | | swrast: fix unmatched span->array->ChanType | Yuanhan Liu | 2011-11-21 | 1 | -0/+4 |