summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* r600g/llvm: Don't feed LLVM output through r600_bytecode_build()Tom Stellard2013-05-064-395/+21
| | | | | The LLVM backend emits raw ISA now, so we can just its output unmodified.
* r600g/llvm: Don't emit CALL_FS for vertex shadersTom Stellard2013-05-062-8/+10
| | | | The LLVM backend takes care of this now.
* i965: Lower bitfieldInsert.Matt Turner2013-05-061-0/+4
| | | | | | | | | | | | v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965/vs: Add support for bit instructions.Matt Turner2013-05-064-1/+106
| | | | | | | | | | | v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add support for bit instructions.Matt Turner2013-05-065-0/+142
| | | | | | | | | | | | Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965: Add support for emitting and disassembling bit instructions.Matt Turner2013-05-064-0/+28
| | | | | | | | | | | | Specifically bfe - for bitfieldExtract() bfi1 and bfi2 - for bitfieldInsert() bfrev - for bitfieldReverse() cbit - for bitCount() fbh - for findMSB() fbl - for findLSB() Reviewed-by: Chris Forbes <[email protected]>
* i965: Print the correct dst and shared-src types for 3-src instructions.Matt Turner2013-05-061-4/+22
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/gen7: Set src/dst types for 3-src instructions.Matt Turner2013-05-061-4/+36
| | | | | | | | | | | | Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <[email protected]> [v1]
* i965: Add 3-src destination and shared-source type macros.Matt Turner2013-05-061-0/+11
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965: Add Gen7+ fields to brw_instruction and add comments.Matt Turner2013-05-061-12/+19
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add a pass to lower bitfield-insert into bfm+bfi.Matt Turner2013-05-067-0/+76
| | | | | | | | | | i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement bitfieldInsert() from ARB_gpu_shader5. v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp. Remove spurious temporary assignment and dereference. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add constant evaluation of bit built-ins.Matt Turner2013-05-061-1/+125
| | | | | | | | v2: Order bits from LSB end (31 - count) for ir_unop_find_msb. v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type == op[1]->type assertion in ir_constant_expression.cpp. Reviewed-by: Chris Forbes <[email protected]> [v2]
* glsl: Add support for new bit built-ins in ARB_gpu_shader5.Matt Turner2013-05-066-5/+71
| | | | | | v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.Matt Turner2013-05-067-0/+342
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Rework ir_reader to handle expressions with four operands.Matt Turner2013-05-061-4/+6
| | | | | | | Needed to support the bitfieldInsert() built-in added by ARB_gpu_shader5. Reviewed-by: Chris Forbes <[email protected]>
* mesa: Add infrastructure for ARB_gpu_shader5.Matt Turner2013-05-067-0/+10
| | | | Reviewed-by: Chris Forbes <[email protected]>
* radeon/llvm: Always build libradeonllvm as staticTom Stellard2013-05-063-17/+10
| | | | | | | | | This library is very small, so there is not much to gain from building it as a shared library. Also, when linking statically with LLVM, a shared libradeonllvm exports LLVM symbols and creates problems when used with other shared objects that also link statically to LLVM. Reviewed-by: [email protected]
* radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2Tom Stellard2013-05-065-203/+173
| | | | | | | | | | | The LLVM C API is considered stable and should never change, so it is much more desirable to use than the LLVM C++ API, which is constantly in flux. v2: - Split target initialization and lookup into separate functions Reviewed-by: [email protected]
* gallivm: Move LLVMStartMultithreaded() static initializer into gallivmTom Stellard2013-05-062-14/+15
| | | | | | | This does not solve all of the problems with using LLVM in a multithreaded enivronment, but it should help in some cases. Reviewed-by: [email protected]
* radeon/llvm: Don't use the global context when parsing LLVM IRTom Stellard2013-05-061-2/+3
| | | | | | | This leads to crashes when multiple threads try to compile compute shaders in the same time. Fixes a crash in bfgminer when using more than one thread.
* i965: Remove GL_ARB_color_buffer_float from GL core contexts.Eric Anholt2013-05-061-1/+2
| | | | | | | | | Of the 3 controls in the extension, one was kept in GL core and the other two were explicitly deprecated and the reasonable default behavior was encoded in the spec. By not exposing the extension, we avoid shader recompiles when switching between float and unorm color buffers. Reviewed-by: Kenneth Graunke <[email protected]>
* r600g/llvm: Update radeon family mappings for LLVM backendTom Stellard2013-05-062-4/+8
| | | | | New processors were added to the backend to distinguish between GPUs with and without vertex caches.
* android: libsync is needed on Android 4.2+ for any driverChia-I Wu2013-05-061-5/+3
| | | | | | | | Add libsync not only for MESA_BUILD_CLASSIC, but also for MESA_BUILD_GALLIUM. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* android: add ilo to the build systemChia-I Wu2013-05-065-0/+93
| | | | | | | | | It can be selected with BOARD_GPU_DRIVERS := ilo Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* glsl: Flip around "if" statements with empty "then" blocks.Eric Anholt2013-05-051-1/+26
| | | | | | | | | | | | This cleans up some funny-looking code in some unigine shaders I was looking at. Also slightly helps on planeshift and a few shaders in an upcoming Valve release. total instructions in shared programs: 1653715 -> 1653587 (-0.01%) instructions in affected programs: 16550 -> 16422 (-0.77%) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ilo: correctly set return types of sampler messagesChia-I Wu2013-05-052-0/+3
| | | | | Correctly set the types of the temporaries. We do not want type conversions when moving the results to the final destinations.
* r600g/llvm: Undefines unrequired texture coord valuesVincent Lejeune2013-05-041-1/+28
| | | | | This is a port of "r600g:mask unused source components for SAMPLE" patch from Vadim Girlin.
* nvc0: fixup video decoding with 2D_ARRAYMaarten Lankhorst2013-05-042-5/+4
| | | | Signed-off-by: Maarten Lankhorst <[email protected]>
* gallium: fix type of flags in pipe_context::flush()Chia-I Wu2013-05-0425-26/+28
| | | | | | | | | | | | | | | | It should be unsigned, not enum pipe_flush_flags. Fixed a build error: src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error: invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive] v2: replace all occurrences of enum pipe_flush_flags by unsigned Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> [olv: document the parameter now that the type is unsigned]
* i965: Enable fast clears on non-8x4-aligned sizes.Eric Anholt2013-05-031-13/+0
| | | | | | | | | | | | Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11). The workaround was to avoid bad primitive/surface sizes, but that's worked around as of a14dc4f92cdad6177d83f051a088a66e31a973bc. (One might note that pre-gen7 we don't know that the right half of an 8x4 at the right edge is actually our pixels, but we're already clobbering those pixels for depth resolves anyway and more work would be required to avoid that). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* vbo: add comments, const qualifiersBrian Paul2013-05-032-9/+24
| | | | Reviewed-by: José Fonseca <[email protected]>
* mesa: whitespace, formatting fixes, etc in api_arrayelt.cBrian Paul2013-05-031-35/+65
| | | | Reviewed-by: José Fonseca <[email protected]>
* vbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()Brian Paul2013-05-031-2/+7
| | | | | | As we do for the other commands which can appear between glBegin/End. Reviewed-by: José Fonseca <[email protected]>
* mesa: change ctx->Driver.NeedFlush to GLbitfield and update commentBrian Paul2013-05-031-3/+3
| | | | Reviewed-by: José Fonseca <[email protected]>
* mesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.Brian Paul2013-05-032-5/+6
| | | | Reviewed-by: José Fonseca <[email protected]>
* vbo: update comments for vbo_save_NotifyBegin()Brian Paul2013-05-031-2/+10
| | | | Reviewed-by: José Fonseca <[email protected]>
* vbo: implement primitive merging for glBegin/End sequencesBrian Paul2013-05-032-14/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A surprising number of apps and benchmarks have poor code like this: glBegin(GL_LINE_STRIP); glVertex(v1); glVertex(v2); glEnd(); // Possibly some no-op state changes here glBegin(GL_LINE_STRIP); glVertex(v3); glVertex(v4); glEnd(); // repeat many, many times. The above sequence can be converted into: glBegin(GL_LINES); glVertex(v1); glVertex(v2); glVertex(v3); glVertex(v4); glEnd(); Similarly for GL_POINTS, GL_TRIANGLES, etc. Merging was already implemented for GL_QUADS in the display list code. Now other prim types are handled and it's also done for immediate mode. In one case: before after ----------------------------------------------- number of st_draw_vbo() calls: 141 45 number of _mesa_prims issued: 7520 632 Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* vbo: create a few utility functions for merging primitivesBrian Paul2013-05-032-0/+109
| | | | | | | To be used by following commit. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* draw/pt: adjust overflow calculationsZack Rusin2013-05-032-2/+8
| | | | | | | | | gallium lies. buffer_size is not actually buffer_size but available size, which is 'buffer_size - buffer_offset' so by adding buffer offset we'd incorrectly compute overflow. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* tgsi/ureg: make the dst register match the src indirectionZack Rusin2013-05-032-4/+11
| | | | | | | | | | | In ureg src registers could have an indirect register that was either a temp or an addr register, while dst registers allowed only addr. That made moving between them a little difficult so make them behave the same way and allow temp's and addr registers as indirect files for both (tgsi supports it, just ureg didn't). Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* gallium: tgsi documentation updates and clarification for integer opcodes.Roland Scheidegger2013-05-031-73/+289
| | | | | | | A lot of them were missing. Others were moved from the Compute ISA to a new Integer ISA section as that seemed more appropriate. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: get rid of depth swizzling.Roland Scheidegger2013-05-037-273/+414
| | | | | | | | | | | | | | | Eliminating this we no longer need to copy between linear and swizzled layout. This is probably not quite ideal since it's a bit more work for now, could do some optimizations by moving depth testing outside the fragment shader loop (but tricky for early depth test as we don't have neither the mask nor the interpolated z in the right order handy). The large amount of tile/untile code is no longer needed will be deleted in next commit. No piglit regressions. v2: change a forgotten LAYOUT_NONE to LAYOUT_LINEAR. v3: fix (bogus) uninitialized variable warnings, add comments, fix a bad type Reviewed-by: Jose Fonseca <[email protected]>
* r600g: Correctly initialize the shader key, v2Lauri Kasanen2013-05-031-1/+2
| | | | | | | | | | | | | | | | | | | | | Assigning a struct only copies the members - any padding is left as is. Thus this code: struct foo_t foo; foo = bar; leaves the padding of foo intact, ie uninitialized random garbage. This patch fixes constant shader recompiles by initializing the struct to zero. For completeness, memcpy is used to copy the key to the shader struct. NOTE: This is a candidate for the stable branches. Signed-off-by: Lauri Kasanen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Andreas Boll <[email protected]>
* st/xvmc/tests: Fix build failure, v2Lauri Kasanen2013-05-031-1/+1
| | | | | | | | | v2: Removed extra libs as requested by Matt Turner. Signed-off-by: Lauri Kasanen <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Andreas Boll <[email protected]>
* scons: remove nouveau buildAndreas Boll2013-05-035-58/+0
| | | | | | | One build system for linux/unix only drivers should be enough. Additionally the nouveau target was disabled anyway. Acked-by: Jose Fonseca <[email protected]>
* scons: remove radeon buildAndreas Boll2013-05-039-185/+0
| | | | | | | | One build system for linux/unix only drivers should be enough. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48694 Acked-by: Jose Fonseca <[email protected]>
* r600g: don't emit surface_sync after FLUSH_AND_INV_EVENTAlex Deucher2013-05-031-26/+0
| | | | | | | | | | | | | | | | | It shouldn't be needed since the FLUSH_AND_INV_EVENT has already made sure the destination caches are flushed. Additionally, we didn't previously emit the surface_sync until this commit: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b Emitting them together causes hangs in compute on cayman/TN and hangs in Heaven on evergreen. Note: this patch is a candidate for the 9.1 branch, but requires: http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a as well. Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g/sb: zero-initialize bytecode structsVadim Girlin2013-05-032-3/+6
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix constant propagation in gvn passVadim Girlin2013-05-031-1/+2
| | | | | | Fixes the bug that prevented propagation of literals in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: don't run unnecessary passesVadim Girlin2013-05-031-3/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 12:31:14 +0000