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* gallium: separate out floating-point CAPs into its own enumMarek Olšák2011-11-2222-130/+157
* gallium: remove PIPE_CAP_GLSL and enable GLSL unconditionallyMarek Olšák2011-11-2215-52/+12
* glsl: convervative_depth is not allowed in the vertex shaderMarek Olšák2011-11-221-2/+2
* glsl: finish up ARB_conservative_depth (v2)Marek Olšák2011-11-223-4/+16
* mesa: rename the AMD_conservative_depth extension flag to ARBMarek Olšák2011-11-224-6/+6
* st/mesa: quick fix of CopyPixels with GL_DEPTH_STENCILMarek Olšák2011-11-221-0/+7
* linker: Remove erroneous multiply by 4 in uniform usage calculationIan Romanick2011-11-221-5/+5
* Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesaChad Versace2011-11-2242-792/+2130
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| * i965/gen6: Enable HiZ by defaultChad Versace2011-11-221-6/+2
| * intel: Use separate stencil whenever possibleChad Versace2011-11-222-2/+2
| * i965: Implement the actual tables for texture alignment units [v2]Kenneth Graunke2011-11-223-13/+105
| * i965/gen6: Set vertical alignment in SURFACE_STATE batchChad Versace2011-11-222-6/+11
| * intel: Store miptree alignment units in the miptreeChad Versace2011-11-224-32/+26
| * intel: Enable HiZ for texture renderbuffersChad Versace2011-11-221-0/+7
| * intel: Resolve buffers in intel_map_renderbuffer()Chad Versace2011-11-221-0/+5
| * intel: Resolve buffers in intel_map_texture_image()Chad Versace2011-11-221-0/+5
| * intel: Mark needed resolves when first enabling HiZ on a miptreeChad Versace2011-11-221-1/+20
| * i965: Mark that depth buffer needs depth resolve after drawingChad Versace2011-11-221-0/+23
| * intel: Resolve buffers in intelSpanRenderStartChad Versace2011-11-221-1/+39
| * intel: Refactor intelSpanRenderStartChad Versace2011-11-221-16/+25
| * i965: Resolve buffers before drawing [v2]Chad Versace2011-11-221-0/+73
| * i965: Prevent recursive calls to FLUSH_VERTICES [v2]Chad Versace2011-11-221-0/+66
| * i965/gen6: Manipulate state batches for HiZ meta-ops [v4]Chad Versace2011-11-228-9/+74
| * i965/gen6: Complete stubs for HiZ buffer resolvesChad Versace2011-11-221-2/+298
| * i965: Add HiZ operation state to brw_contextChad Versace2011-11-221-0/+35
| * intel: Add resolve functions for renderbuffersChad Versace2011-11-222-0/+94
| * intel: Add resolve functions for miptreesChad Versace2011-11-222-1/+174
| * intel: Add field intel_mipmap_tree::hiz_mapChad Versace2011-11-221-0/+13
| * intel: Define struct intel_resolve_map [v2]Chad Versace2011-11-224-0/+196
| * intel: Change signature of HiZ resolve functionsChad Versace2011-11-224-19/+32
| * intel: Remove unused HiZ functionsChad Versace2011-11-223-27/+0
| * intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]Chad Versace2011-11-225-30/+50
| * intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stenc...Chad Versace2011-11-226-236/+252
| * intel: Refactor intel_render_texture() [v2]Chad Versace2011-11-221-33/+88
| * intel: Define intel_miptree_check_level_layer()Chad Versace2011-11-221-0/+13
| * intel: Remove unneeded params from intel_renderbuffer_set_draw_offset()Chad Versace2011-11-223-14/+10
| * intel: Track the miptree layer wrapped by a renderbuffer [v2]Chad Versace2011-11-222-5/+49
| * intel: Kill intel_mipmap_level::nr_images [v4]Chad Versace2011-11-226-43/+57
| * intel: Refactor intel_miptree_copy_teximage()Chad Versace2011-11-211-56/+66
| * intel: Refactor intel_mipmap_level offsetsChad Versace2011-11-212-25/+37
| * intel: Replace intel_renderbuffer::region with a miptree [v3]Chad Versace2011-11-2116-140/+203
| * intel: Define intel_miptree_create_for_renderbuffer()Chad Versace2011-11-212-0/+36
| * intel: Move inline functions from intel_fbo.h to .cChad Versace2011-11-212-17/+23
| * intel: Kill intel_framebuffer_get_hiz_region()Chad Versace2011-11-211-17/+3
| * intel: Temporarily disable HiZ for texturesChad Versace2011-11-211-59/+3
| * intel: Always gather stencil buffer in intel_map_renderbuffer_separate_s8z24()Chad Versace2011-11-211-32/+20
| * intel: Fix swrast_render_start() for depthstencil buffers with separate stencilChad Versace2011-11-212-29/+15
| * intel: Don't use special stencil span accessorsChad Versace2011-11-211-42/+1
| * nvc0: add support for GF119 (NVD9)Ben Skeggs2011-11-182-0/+2
* | i915g: implement RGBX and BGRX render targetsVasily Khoruzhick2011-11-222-2/+7
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