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* ac/nir: consolidate setting userdata locationDave Airlie2017-06-071-28/+17
| | | | | | | | Just pass a pointer and increment inside the function, makes the code less error prone. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glthread: remove extra _mesa_glthread_finish() from generated codeTimothy Arceri2017-06-071-1/+1
| | | | | | | | | | | The other user of print_sync_dispatch() was ending up with code that looked like: _mesa_glthread_finish(ctx); _mesa_glthread_restore_dispatch(ctx); _mesa_glthread_finish(ctx); Reviewed-by: Marek Olšák <[email protected]>
* intel: Fix broxton 2x6 way size computationAnuj Phogat2017-06-061-0/+4
| | | | | | | | | | | | | | | | | This patch is undoing the changes to way size computation in broxton 2x6, made by below commit: Commit: 0d576fbfbe912cf3fb9ab594bb31eb58bccf2138 Author: Anuj Phogat <[email protected]> i965: Simplify l3 way size computations By making use of l3_banks field in gen_device_info struct l3_way_size for gen7+ = 2 * l3_banks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306 Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Mark Janes <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* radv: move chip_class extraction down further.Dave Airlie2017-06-071-1/+2
| | | | | | | | This seems to matter here in a profile, without this we spend a lot more time exiting this function with no flush bits. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move lots of index related things into the bind.Dave Airlie2017-06-072-19/+14
| | | | | | | | This just moves lots of stuff to the bind stage rather than dealing with it in the draw stage. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: move calculating the vertex sgpr to the pipeline.Dave Airlie2017-06-073-41/+34
| | | | | | | There is no need to calculate this at draw time. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rename and make global some functions.Dave Airlie2017-06-072-12/+17
| | | | | | | I want to use these in the pipeline setup stage. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tree-wide: remove trailing backslashEric Engestrom2017-06-0715-16/+16
| | | | | | | | | Simple search for a backslash followed by two newlines. If one of the newlines were to be removed, this would cause issues, so let's just remove these trailing backslashes. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radv/gfx9: use correct register setting for uconfig regsDave Airlie2017-06-071-4/+4
| | | | | | Thanks to Marek for pointing this out. Signed-off-by: Dave Airlie <[email protected]>
* radv: Remove SI num RB override for occlusion queries.Bas Nieuwenhuizen2017-06-061-3/+0
| | | | | | | | radeonsi doesn't have it anymore either. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Dave Airlie <[email protected]>
* radv: Split out updating the vertex descriptors.Bas Nieuwenhuizen2017-06-061-11/+18
| | | | | | | Simple refactor. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Move pipeline stuff from flush_state to emit_graphics_pipeline.Bas Nieuwenhuizen2017-06-061-11/+10
| | | | | | | No functional changes. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Add early exit for cache flushes.Bas Nieuwenhuizen2017-06-061-2/+4
| | | | | | | | No sense checking each bit separately in the common case of none being set. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Remove vertex_descriptors_dirty.Bas Nieuwenhuizen2017-06-062-4/+1
| | | | | | | Redundant. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Don't use a divide by index_size.Bas Nieuwenhuizen2017-06-061-3/+8
| | | | | | | Divides are pretty slow, and this is in the hot path of a draw. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.Chris Wilson2017-06-063-0/+33
| | | | | | | | | | | The manual detiling paths are not prepared to handle Gen4-G45 with swizzling enabled, so explicitly disable them. (They're already disabled because these platforms don't have LLC but a future patch could enable this path). Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Remove brw_bo_map_unsynchronized()Matt Turner2017-06-063-23/+2
| | | | | | Call brw_bo_map() directly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use unsynchronized mappings for BufferSubData on non-LLCMatt Turner2017-06-061-10/+6
| | | | | | | | | | | Now that unsynchronized maps actually work, we can use them, like we do on LLC platforms. On Broxton, the performance of Unigine Valley 1.1-rc1 is improved by 37.6656% +/- 0.401389% (n=20) at 1280x720/QUALITY_LOW, and by 20.862% +/- 2.20901% (n=3) at 1920x1080/QUALITY_LOW. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make unsynchronized maps unsynchronized on non-LLCMatt Turner2017-06-062-22/+3
| | | | | | | | On Broxton, the performance of Unigine Valley 1.0 is improved by 13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by 1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNCMatt Turner2017-06-061-40/+9
| | | | | | | | | | | | This way we can let brw_bo_map() choose the best mapping type. Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized() to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have the same behavior previously provided by brw_bo_map_unsynchronized(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Elide call to set_domain() if MAP_ASYNCMatt Turner2017-06-061-4/+8
| | | | | | No functional change (no callers currently pass MAP_ASYNC) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add and use brw_bo_map()Matt Turner2017-06-0616-54/+52
| | | | | | | | | | | | We can encapsulate the logic for choosing the mapping type. This will also help when we add WC mappings. A few functional changes are made in this patch. On non-LLC, what were previously WB mappings are now GTT mappings (in the prefilling debug code in brw_performance_query.c; the shader_time code in brw_program.c; and in the case of an RW mapping in intel_buffer_objects.c). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop MAP_READ from some write-only mappingsMatt Turner2017-06-064-4/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass flags to brw_bo_map_*Matt Turner2017-06-0616-33/+49
| | | | | | | | | | | | | brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear whether we were also planning to read from the buffer. I kept everything semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE depending on the write_enable argument. The other flags are not used yet, but MAP_ASYNC for instance, will be used in a later patch to remove the need for a separate brw_bo_map_unsynchronized() function. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename brw_bo_map() -> brw_bo_map_cpu()Matt Turner2017-06-0616-29/+30
| | | | | | | | I'm going to make a new function named brw_bo_map() in a later patch that is responsible for choosing the mapping type, so this patch clears the way. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename *_virtual -> map_*Matt Turner2017-06-062-31/+31
| | | | | | | I think these are better names, and it reduces the delta between upstream and Chris Wilson's brw-batch branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass the map-mode along to intel_mipmap_tree_map_raw()Chris Wilson2017-06-061-13/+16
| | | | | | | | Since we can distinguish when mapping between READ and WRITE, we can pass along the map mode to avoid stalls and flushes where possible. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a cache_coherent field to brw_boMatt Turner2017-06-063-0/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused 'use_resource_streamer' fieldMatt Turner2017-06-061-1/+0
| | | | | | Missing in the resource streamer removal of commit 951f56cd43bc. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove brw_bo's virtual memberMatt Turner2017-06-0617-121/+102
| | | | | | Just return the map from brw_map_bo_* Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused brw_bo_map__* functionsMatt Turner2017-06-062-109/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Set better descriptor set limitsAlex Smith2017-06-061-3/+6
| | | | | | | | | | | | | Based on discussions with Jason, Ivy Bridge and Bay Trail only actually support 16 samplers, while newer hardware can support more than the current limit of 64. Therefore set the lower limit where needed, and bump up to 128 for everything else. There is also a limit on the total number of other resources of around 250. This allows Dawn of War III to render correctly on ANV. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: Set driver version to Mesa versionAlex Smith2017-06-061-1/+1
| | | | | | | | | | | | As already done by RADV. v2: Move version calculation function to src/vulkan/util to share with RADV. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv/vulkan: Move radv_get_driver_version to src/vulkan/utilAlex Smith2017-06-064-23/+53
| | | | | | | | | | | | This means it can be reused for other Vulkan drivers. Also fix up a typo, need to search for '.' in the version string rather than ','. v2: Remove unneeded temporary version variable (Emil, Eric) Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* util/vulkan: Move Vulkan utilities to src/vulkan/utilAlex Smith2017-06-0621-19/+29
| | | | | | | | | | | | | We have Vulkan utilities in both src/util and src/vulkan/util. The latter seems a more appropriate place for Vulkan-specific things, so move them there. v2: Android build system changes (from Tapani Pälli) Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* intel: gen-decoder: rework how we handle groupsLionel Landwerlin2017-06-063-104/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current way of handling groups doesn't seem to be able to handle MI_LOAD_REGISTER_* with more than one register. This change reworks the way we handle groups by building a traversal list on loading the GENXML files. Let's say you have Instruction { Field0 Field1 Field2 Group0 (count=2) { Field0-0 Field0-1 } Group1 (count=4) { Field1-0 Field1-1 } } We build of linked on load that goes : Instruction -> Group0 -> Group1 All of those are gen_group structures, making the traversal trivial. We just need to iterate groups for the right number of timers (count field in genxml). The more fancy case is when you have only a single group of unknown size (count=0). In that case we keep on reading that group for as long as we're within the DWordLength of that instruction. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radeonsi: fix a GPU hang with tessellation on 2-CU configsMarek Olšák2017-06-061-1/+5
| | | | | | | | | Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced to 2 CUs. Cc: 17.0 17.1 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* mesa: make use of NewWindowRectangles driver flagsSamuel Pitoiset2017-06-062-3/+5
| | | | | | | | Now, st_update_window_rectangles() won't be called when the scissor is going to be updated. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add new gl_driver_flags::NewWindowRectanglesSamuel Pitoiset2017-06-061-0/+5
| | | | | | | | | | | | This new driver flag will replace _NEW_SCISSOR which is emitted when setting new window rectangles but it actually triggers useless changes in the state tracker (like scissor and rasterizer). EXT_window_rectangles is currently only supported by Nouveau. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()Samuel Pitoiset2017-06-061-3/+0
| | | | | | | | | This is actually useless because this driver call is only used by the classic DRI drivers which don't support that extension and probably won't never support it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when min sample shading changesSamuel Pitoiset2017-06-061-3/+6
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when sample mask changesSamuel Pitoiset2017-06-061-0/+3
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: only emit _NEW_MULTISAMPLE when coverage parameters changeSamuel Pitoiset2017-06-061-3/+7
| | | | | | | | We usually check that given parameters are different before updating the state. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.Kenneth Graunke2017-06-053-3/+2
| | | | | | | | | We moved to INTEL_SCALAR_* when we added more than a single stage, but never went back and converted the VS to work that way. Be consistent. Also update the documentation to actually mention these debug variables. Acked-by: Jason Ekstrand <[email protected]>
* radv: expose integrated device type for APUs.Dave Airlie2017-06-061-1/+1
| | | | | | | | This just sets the vulkan device type depending on whether this is an APU or GPU. Signed-off-by: Dave Airlie <[email protected]> Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
* ac/surface: Fix HTILE for radv.Bas Nieuwenhuizen2017-06-061-2/+1
| | | | | | | We always compute HTILE size using addrlib, even when not TC compatible. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlied <[email protected]>
* radv: fix write event eop on vega.Dave Airlie2017-06-061-1/+1
| | | | Typo here, fixes command submission hangs on vega
* radv: enable GFX9 on radvDave Airlie2017-06-061-2/+4
| | | | | | | | I'm open to reverting this closer to release if bad things happen, but it might be easier to debugging to leave it for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: turn off geom/tess for gfx9.Dave Airlie2017-06-061-4/+4
| | | | | | | We don't support these yet, and it'll take a bit of work to do so. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: misc GFX9 changes.Dave Airlie2017-06-063-6/+21
| | | | | | | These are just some register changes ported from radeonsi for gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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