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* glsl: Add built-ins from ARB_shader_bit_encoding to ARB_gpu_shader5.Matt Turner2013-08-271-0/+20
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Add support for translating ir_triop_fma into MAD.Matt Turner2013-08-272-0/+12
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add support for translating ir_triop_fma into MAD.Matt Turner2013-08-274-0/+10
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Assert that ir_expressions are usable by 3-src instructions.Matt Turner2013-08-271-0/+1
| | | | | | | MAD will be generated directly from ir_triop_fma, so this assertion checks that all ir_expressions are usable. Reviewed-by: Paul Berry <[email protected]>
* glsl: Add support for new fma built-in in ARB_gpu_shader5.Matt Turner2013-08-276-0/+22
| | | | | | v2: Add constant folding support. Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Add new fma built-in IR and prototype from ARB_gpu_shader5.Matt Turner2013-08-272-0/+34
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r300g: enable MSAA on r300-r400, be careful about using color compressionMarek Olšák2013-08-274-5/+14
| | | | | | | | | | MSAA was tested by one user on RS690 and it works for him with color compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM. Since we don't have hardware documentation about which chipsets actually have CMASK RAM, I had to take a guess based on the presence of HiZ. Reviewed-by: Alex Deucher <[email protected]>
* draw: clean up setting stream out information a bitRoland Scheidegger2013-08-279-34/+39
| | | | | | | | | | | | | | | | | In particular noone is interested in the vertex count, so drop that, and also drop the duplicated num_primitives_generated / so.primitives_storage_needed variables in drivers. I am unable for now to figure out if primitives_storage_needed in SO stats (used for d3d10) should increase if SO is disabled, though the equivalent num_primitives_generated used for OpenGL definitely should increase. In any case we were only counting when SO is active both in softpipe and llvmpipe anyway so don't pretend there's an independent num_primitives_generated counter which would count always. (This means the PIPE_QUERY_PRIMITIVES_GENERATED count will still be wrong just as before, should eventually fix this by doing either separate counting for this query or adjust the code so it always counts this even if SO is inactive depending on what's correct for d3d10.) Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-273-18/+20
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* softpipe: support nested/overlapping queries for all query typesRoland Scheidegger2013-08-272-18/+17
| | | | | | | There's just no way resetting the counters is working with nested/overlapping queries. Reviewed-by: Brian Paul <[email protected]>
* glsl: Disallow uniform block layout qualifiers on non-uniform block vars.Matt Turner2013-08-261-4/+13
| | | | | | Cc: 9.2 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68460 Reviewed-by: Ian Romanick <[email protected]>
* i915: Optimize SEQ and SNE when two operands are uniformsIan Romanick2013-08-261-12/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SEQ and SNE are not native i915 instructions, so they each generate at least 3 instructions. If both operands are uniforms or constants, we get 5 instructions like: U[1] = MOV CONST[1] U[0].xyz = SGE CONST[0].xxxx, U[1] U[1] = MOV CONST[1].-x-y-z-w R[0].xyz = SGE CONST[0].-x-x-x-x, U[1] R[0].xyz = MUL R[0], U[0] This code is stupid. Instead of having the individual calls to i915_emit_arith generate the moves to utemps, do it in the caller. This results in code like: U[1] = MOV CONST[1] U[0].xyz = SGE CONST[0].xxxx, U[1] R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w R[0].xyz = MUL R[0], U[0] This allows fs-temp-array-mat2-index-col-wr and fs-temp-array-mat2-index-row-wr to fit in hardware limits (instead of falling back to software rasterization). NOTE: Without pending patches to the piglit tests, these tests will now fail. This is an unrelated, pre-existing issue. v2: Copy most of the body of the commit message into comments in the code. Suggested by Eric. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copiesTom Stellard2013-08-261-1/+1
| | | | | | CC: "9.2" <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/clover: Add event to deps even if it has been triggeredNiels Ole Salscheider2013-08-261-1/+1
| | | | | | | | The command is submitted once the event has been triggered, but it might not have completed yet. Therefore, we have to add it to deps in order to wait on it. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/clover: Profiling supportNiels Ole Salscheider2013-08-263-18/+142
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* tgsi_build: fix order of arguments for ind register buildDave Airlie2013-08-271-1/+1
| | | | | | | This was broken when arrayid was added. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: finish declaration parsing for arrays.Dave Airlie2013-08-271-1/+31
| | | | | | | | | I previously fixed this partly in 9e8400f4c95bde1f955c7977066583b507159a10, however I didn't go far enough in testing it, now when I parse a TGSI shader with arrays in it my iterator can see the ArrayID set to the proper value. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: replace 0 with PIPE_OK in a few placesBrian Paul2013-08-263-5/+5
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* swrast: init i0, i1 values to silence warningsBrian Paul2013-08-261-0/+1
| | | | Reviewed-by: Chad Versace <[email protected]>
* mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT()Brian Paul2013-08-261-1/+2
| | | | | | to silence gcc 4.8.1 warnings. And improve the ASSERT(0) call. Reviewed-by: Chad Versace <[email protected]>
* glsl: init limit=0 to silence uninitialized var warningBrian Paul2013-08-261-1/+1
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Allocate register set once at context creation.Kenneth Graunke2013-08-263-4/+6
| | | | | | | | | | Now that we use a fixed set of register classes, we can set up the register set and conflict graphs once, at context creation, rather than on every VS compile. This is obviously less expensive, and also what we already do in the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Move base_reg_count computation to brw_alloc_reg_set().Kenneth Graunke2013-08-261-3/+4
| | | | | | | | We're soon going to be calling brw_alloc_reg_set() from outside of the visitor, where we don't have the precomputed "max_grf" variable handy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Expose the payload registers to the register allocator.Kenneth Graunke2013-08-262-6/+36
| | | | | | | | | | | | | | | For now, nothing else can get allocated over them. That may change at some point in the future. This also means that base_reg_count can be computed without knowing the number of registers used for the payload, which is required if we want to allocate the register set once at context creation time. See commit 551e1cd44f6857f7e29ea4c8f892da5a97844377, which implemented virtually identical code in the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Use a fixed set of register classes.Kenneth Graunke2013-08-261-37/+13
| | | | | | | | | | | Arrays, structures, and matrices use large VGRFs of arbitrary sizes. However, split_virtual_grfs() breaks those down into VGRFs of size 1. For reference, commit 5d90b988791e51cfb6413109271ad102fd7a304c is the analogous change to the FS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Allow C++ type safety in the use of enum brw_urb_write_flags.Paul Berry2013-08-267-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (From a suggestion by Francisco Jerez) If an enum represents a bitfield of flags, e.g.: enum E { A = 1, B = 2, C = 4, D = 8, }; then C++ normally prohibits statements like this: enum E x = A | B; because A and B are implicitly converted to ints before OR-ing them, and an int can't be stored in an enum without a type cast. C, on the other hand, allows an int to be implicitly converted to an enum without casting. In the past we've dealt with this situation by storing flag bitfields as ints. This avoids ugly casting at the expense of some type safety that C++ would normally have offered (e.g. we get no warning if we accidentally use the wrong enum type). However, we can get the best of both worlds if we override the | operator. The ugly casting is confined to the operator overload, and we still get the benefit of C++ making sure we don't use the wrong enum type. v2: Remove unnecessary comment and unnecessary use of "enum" keyword. Use static_cast. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Remove redundant (and uninitialized) field vec4_generator::ctx.Paul Berry2013-08-262-3/+2
| | | | | | | | | | | | | We never noticed that this field was uninitialized because it is only used in an error path that reports internal Mesa errors. But it's silly to have it around anyway because &brw->ctx is equivalent. Should fix Coverity defect CID 1063351: Uninitialized pointer field (UNINIT_CTOR) /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp: 148 Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't try to fall back when creating unrecognized program targets.Paul Berry2013-08-261-1/+2
| | | | | | | | | | | | | | If brwNewProgram is asked to create a program for an unrecognized target, don't bother falling back on _mesa_new_program(). That just hides bugs. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> v2: Use assert() rather than _mesa_problem(). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* radeonsi: Also set the depth component mask bit for stencil-only exportsMichel Dänzer2013-08-261-1/+4
| | | | | | | | The stencil values come out wrong without this for some reason. 50 more little piglits. Cc: [email protected]
* glsl: Add built-in function prototypes for GLSL 3.30Kenneth Graunke2013-08-252-0/+1169
| | | | | | | | 330.frag is a direct copy of 150.frag. 330.glsl is 150.glsl combined with ARB_shader_bit_encoding.glsl. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Bump standalone compiler versions to 3.30.Kenneth Graunke2013-08-252-3/+3
| | | | | | | These are necessary in order to compile the built-in functions. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Set query->EverBound in glQueryCounter().Kenneth Graunke2013-08-251-0/+1
| | | | | | | | | | | | | | | | | | | | | glIsQuery is supposed to return false for names returned by glGenQueries until their first use. BeginQuery is a use, but QueryCounter is also a use. From the ARB_timer_query spec: "A timer query object is created with the command void QueryCounter(uint id, enum target); [...] If <id> is an unused query object name, the name is marked as used [...]" Fixes Piglit's spec/ARB_timer_query/query-lifetime. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]> Cc: [email protected]
* r600g: Implement the new float comparison instructions for Cayman as well.Henri Verbeet2013-08-251-4/+4
| | | | | | | | I assume this should have been part of commit 7727fbb7c5d64348994bce6682e681d6181a91e9. This (obviously) fixes a lot tests. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv30: add forgotten PIPE_CAP_CUBE_MAP_ARRAY cap to listIlia Mirkin2013-08-251-0/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "9.2" <[email protected]>
* nouveau/video: avoid overwriting base codec init with templateIlia Mirkin2013-08-252-2/+2
| | | | | | | | | | Commit 53e20b8b introduced the use of a template to initialize some common fields. Move this copying of fields to before the common vp3 fields are initialized. Reported-by: Martin Peres <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Christian König <[email protected]>
* freedreno/a3xx: don't leak so muchRob Clark2013-08-241-0/+11
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix SGT/SLT/etcRob Clark2013-08-241-29/+125
| | | | | | | | | | The cmps.f.* instruction doesn't actually seem to give a float 1.0 or 0.0 output. It either needs a cov.u16f16 or add.s + sel.f16. This makes SGT/SLT/etc more similar to CMP, so handle them in trans_cmp(). This fixes a bunch of piglit tests. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: bit of re-arrange/cleanupRob Clark2013-08-241-61/+71
| | | | | | | | It seems there are a number of cases where instructions have limitations about taking reading src's from const register file, so make get_unconst() a bit easier to use. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: make compiler errors more usefulRob Clark2013-08-242-17/+33
| | | | | | | | | | | | | | We probably should get rid of assert() entirely, but at this stage it is more useful for things to crash where we can catch it in a debugger. With compile_error() we have a single place to set an error flag (to bail out and return an error on the next instruction) so that will be a small change later when enough of the compiler bugs are sorted. But re-arrange/cleanup the error/assert stuff so we at least get a dump of the TGSI that triggered it. So we see some useful output in piglit logs. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix segfault when no color buffer boundRob Clark2013-08-247-18/+40
| | | | | | | Don't crash when no color buffer bound. Something caught when starting to run piglit, fixes a hanful of piglit tests. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: cat4 cannot use const reg as srcRob Clark2013-08-241-10/+27
| | | | | | | | | | | | | Category 4 instructions (rsq, rcp, sqrt, etc) seem to be unable to take a const register as src. In these cases we need to move the src to a temporary gpr first. This is the second case of such a restriction, where the instruction encoding appears to support a const src, but in fact the hw appears to ignore that bit. So split things out into a helper that can be re-used for any instructions which have this limitation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: use max_reg rather than file_countRob Clark2013-08-241-7/+7
| | | | | | | | | | Our current (rather naive) register assignment is based on mapping different register files (INPUT, OUTPUT, TEMP, CONST, etc) based on the max register index of the preceding file. But in some cases, the lowest used register in a file might not be zero. In which case file_count[file] != file_max[file] + 1. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: handle saturate on dstRob Clark2013-08-241-0/+49
| | | | | | | | Sometimes things other than color dst need saturating, like if there is a 'clamp(foo, 0.0, 1.0)'. So for saturated dst add the extra instructions to fix up dst. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: fix CMPRob Clark2013-08-241-2/+2
| | | | | | | | | | | | | | | | The 1st src to add.s needs (r) flag (repeat), otherwise it will end up: add.s dst.xyzw, tmp.xxxx -1 instead of: add.s dst.xyzw, tmp.xyzw, -1 Also, if we are using a temporary dst to avoid clobbering one of the src registers, we actually need to use that as the dst for the sel instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: some texture fixesRob Clark2013-08-241-1/+24
| | | | | | Stop hard coding bits that indicate texture type (2d/3d/cube/etc). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update register headersRob Clark2013-08-248-111/+758
| | | | | | resync w/ rnndb database Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to disable scissor optimizationRob Clark2013-08-243-14/+22
| | | | | | Useful for testing and debugging. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix viewport on gmem->mem resolveRob Clark2013-08-241-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix color inversion on mem->gmem restoreRob Clark2013-08-241-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: Handle additional PIPE_COMPUTE_CAP_*Niels Ole Salscheider2013-08-231-1/+14
| | | | | | | | | | | This patch adds support for: PIPE_COMPUTE_CAP_MAX_INPUT_SIZE PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE Return the values reported by the closed source driver for now. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
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