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* radeonsi: use a compiler queue with a low priority for optimized shadersMarek Olšák2017-06-073-8/+34
* util/u_queue: add an option to set the minimum thread priorityMarek Olšák2017-06-078-8/+29
* radeonsi: decrease the number of compiler threads to num CPUs - 1Marek Olšák2017-06-071-1/+4
* radeonsi: drop unfinished shader compilations when destroying shadersMarek Olšák2017-06-072-3/+5
* util/u_queue: add a way to remove a job when we just want to destroy itMarek Olšák2017-06-072-6/+49
* freedreno/a5xx: set SP_BLEND_CONTROL properlyRob Clark2017-06-073-1/+4
* freedreno/a5xx: LRZ supportRob Clark2017-06-0714-14/+234
* freedreno: drop timestamp fieldRob Clark2017-06-072-3/+0
* freedreno/a5xx: refactor out helper for LRZ flushRob Clark2017-06-073-11/+19
* freedreno: reshuffle FD_MESA_DEBUG bitmaskRob Clark2017-06-071-3/+3
* freedreno: update generated headersRob Clark2017-06-077-17/+31
* gallium/u_blitter: use 2D_ARRAY for cubemap blits if possibleMarek Olšák2017-06-075-22/+39
* gallium/u_blitter: use TXF if possibleMarek Olšák2017-06-071-102/+190
* gallium/u_blitter: use TEX_LZ if it's supportedMarek Olšák2017-06-071-4/+8
* gallium/util: add _LZ and TXF options to simple shadersMarek Olšák2017-06-076-33/+77
* gallium/ureg: add TEX/TXF_LZ opcodes to uregMarek Olšák2017-06-071-0/+2
* i965: Use BLORP for all HiZ opsJason Ekstrand2017-06-073-162/+10
* blorp: Use FullSurfaceDepthandStencilClear for blorp_hiz_opJason Ekstrand2017-06-073-0/+5
* i965: Move the post-HiZ-clear flush/stall to intel_hiz_execJason Ekstrand2017-06-072-16/+18
* intel/blorp: Plumb through access to the workaround BOJason Ekstrand2017-06-073-2/+32
* anv/blorp: Move the depth cache flush outside of BLORPNanley Chery2017-06-072-8/+16
* intel/blorp: Refactor the HiZ op interfaceJason Ekstrand2017-06-074-55/+60
* i965/blorp: Inline gen6_blorp_execJason Ekstrand2017-06-071-18/+11
* i965: Perform HiZ flush/stall prior to HiZ resolvesJason Ekstrand2017-06-071-13/+26
* i965: Move the pre-depth-clear flush/stalls to intel_hiz_execJason Ekstrand2017-06-072-56/+58
* i965/blorp: Take a layer range in intel_hiz_execJason Ekstrand2017-06-075-18/+16
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-0715-137/+91
* dri3/GLX: Fix drawable invalidation v2Thomas Hellstrom2017-06-071-0/+6
* i965: Fix alpha to one with dual color blending.Kenneth Graunke2017-06-071-13/+44
* mesa: add KHR_no_error support for glTexSubImage*D()Samuel Pitoiset2017-06-073-3/+64
* mesa: add texsubimage() helperSamuel Pitoiset2017-06-071-0/+18
* mesa: make _mesa_texture_sub_image() staticSamuel Pitoiset2017-06-071-20/+20
* mesa: rename texsubimage() to texsubimage_err()Samuel Pitoiset2017-06-071-17/+17
* mesa: add KHR_no_error support for glCopyImageSubData()Samuel Pitoiset2017-06-073-1/+31
* mesa: add copy_image_subdata() helperSamuel Pitoiset2017-06-071-31/+45
* mesa: add prepare_target() helperSamuel Pitoiset2017-06-071-0/+24
* mesa: rename prepare_target() to prepare_target_err()Samuel Pitoiset2017-06-071-16/+18
* mesa: add KHR_no_error support for glBlitNamedFramebuffer()Samuel Pitoiset2017-06-072-0/+27
* mesa: add blit_named_framebuffer() helperSamuel Pitoiset2017-06-071-31/+54
* mesa: add KHR_no_error support for glBlitFramebuffer()Samuel Pitoiset2017-06-073-1/+22
* mesa: add validate_depth_buffer() helperSamuel Pitoiset2017-06-071-29/+43
* mesa: add validate_stencil_buffer() helperSamuel Pitoiset2017-06-071-34/+47
* mesa: add validate_color_buffer() helperSamuel Pitoiset2017-06-071-61/+77
* mesa: wrap blit_framebuffer() into blit_framebuffer_err()Samuel Pitoiset2017-06-071-9/+25
* mesa: add 'no_error' parameter to blit_framebuffer()Samuel Pitoiset2017-06-071-97/+95
* mesa: make _mesa_blit_framebuffer() staticSamuel Pitoiset2017-06-072-23/+14
* mesa: add KHR_no_error support for glBindBuffer()Samuel Pitoiset2017-06-073-1/+14
* mesa: add KHR_no_error support for glInvalidateBufferData()Samuel Pitoiset2017-06-073-1/+13
* mesa: add KHR_no_error support for glInvalidateBufferSubData()Samuel Pitoiset2017-06-073-1/+16
* mesa: add invalidate_buffer_subdata() helperSamuel Pitoiset2017-06-071-4/+11
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