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* i965: Explicitly set widths on gen5 math instruction destinations.Jason Ekstrand2014-09-301-1/+1
* i965/fs: Make half() divide the register width by 2 and use it moreJason Ekstrand2014-09-302-5/+13
* i965/fs: Add a concept of a width to fs_regJason Ekstrand2014-09-302-4/+78
* i965/fs: A little harmless refactoring of register_coalesceJason Ekstrand2014-09-301-7/+7
* i965/brw_reg: Add a firsthalf function and use it in the generatorJason Ekstrand2014-09-302-29/+44
* i965/fs: Copy propagate partial reads.Jason Ekstrand2014-09-302-20/+64
* i965/fs: Refactor fs_inst::is_send_from_grf()Jason Ekstrand2014-09-301-9/+16
* i965/fs: Clean up emit_fb_writesJason Ekstrand2014-09-302-112/+85
* i965/fs: Print BAD_FILE registers in dump_instructionJason Ekstrand2014-09-301-1/+1
* i965/fs: Make compact_virtual_grfs an optimization passJason Ekstrand2014-09-302-8/+13
* i964/fs: Make immediate fs_reg constructors explicitJason Ekstrand2014-09-304-10/+11
* i965/fs: Make null_reg_* const members of fs_visitor instead of globalsJason Ekstrand2014-09-303-3/+12
* i965/fs: Use the var_from_vgrf helper function instead of doing it manuallyJason Ekstrand2014-09-301-4/+4
* i965/fs: Fix a bug with dead_code_eliminate on large writesJason Ekstrand2014-09-301-1/+1
* i965/fs: Use the UW type for the destination of VARYING_PULL_CONSTANT_LOAD in...Jason Ekstrand2014-09-301-2/+2
* i965/fs: Use offset a lot more placesJason Ekstrand2014-09-304-93/+78
* i965/fs: fix a comment in compact_virtual_grfsJason Ekstrand2014-09-301-1/+1
* i965/fs: Rewrite fs_visitor::split_virtual_grfsJason Ekstrand2014-09-301-47/+86
* i965/fs_live_variables: Use var_from_vgrf insead of repeating the calculationJason Ekstrand2014-09-301-2/+2
* i965/fs: Manually generate the meta fast-clear shaderJason Ekstrand2014-09-302-90/+35
* radeonsi: Pass the slice size to si_dma_copy_bufferMichel Dänzer2014-09-301-4/+4
* radeonsi: Catch more cases that can't be handled by si_dma_copy_buffer/tileMichel Dänzer2014-09-301-3/+11
* radeonsi: Fix si_dma_copy(_tile) for compressed formatsMichel Dänzer2014-09-301-2/+2
* radeonsi: Fix tiling mode index for stencil resourcesMichel Dänzer2014-09-301-2/+3
* ilo: fix format of edge flag pointerChia-I Wu2014-09-301-3/+5
* ilo: add a pass to finalize ilo_ve_stateChia-I Wu2014-09-308-158/+190
* ilo: precalculate aligned depth buffer sizeChia-I Wu2014-09-307-48/+43
* ilo: use dynamic bo for rectlist verticesChia-I Wu2014-09-3010-73/+92
* st/xa: Fix regression in xa_yuv_planar_blit()Thomas Hellstrom2014-09-302-0/+12
* i965: Delete intel_chipset.h.Kenneth Graunke2014-09-295-251/+0
* driconf: Correct and update Catalan translationAlex Henrie2014-09-291-8/+8
* driconf: Update Spanish translationAlex Henrie2014-09-291-5/+5
* driconf: Synchronize po filesAlex Henrie2014-09-296-319/+390
* vc4: Don't try to do stores to buffers that aren't bound.Eric Anholt2014-09-291-5/+8
* vc4: Shove some depth comparison bits down to where they're used.Eric Anholt2014-09-291-5/+5
* i965: Use BRW_MATH_DATA_SCALAR when source regioning is scalar.Matt Turner2014-09-296-11/+9
* i965/compaction: Move variable declarations to their uses.Matt Turner2014-09-291-5/+4
* i965/compaction: Simplify jump target code.Matt Turner2014-09-291-26/+18
* freedreno/a3xx: re-emit shaders on variant changeRob Clark2014-09-292-1/+50
* freedreno/ir3: add some cmdline argsRob Clark2014-09-291-8/+87
* freedreno/a3xx: add support to emulate GL_CLAMPRob Clark2014-09-298-16/+129
* freedreno: add texcoord clamp support to loweringRob Clark2014-09-292-5/+173
* freedreno: move bind_sampler_states to per-generationRob Clark2014-09-294-23/+48
* freedreno/a3xx: fix border color orderRob Clark2014-09-291-5/+4
* freedreno/a3xx: add 32bit integer vtx formatsRob Clark2014-09-292-17/+37
* vc4: Add support for GL 1.1's stupid CLAMP mode.Eric Anholt2014-09-291-4/+19
* vc4: Add support for texture border color.Eric Anholt2014-09-292-1/+84
* vc4: Add the necessary stubs for occlusion queries.Eric Anholt2014-09-294-1/+87
* vc4: Optimize out silly SUBs of 0.Eric Anholt2014-09-291-0/+11
* vc4: Dump constant uniform values in VC4_DEBUG=qir.Eric Anholt2014-09-296-24/+32
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