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* mesa: add blend_equationi() helperSamuel Pitoiset2017-07-311-11/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add KHR_no_error support to glSampleMaski()Samuel Pitoiset2017-07-313-1/+11
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add sample_maski() helperSamuel Pitoiset2017-07-311-6/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add KHR_no_error support to glDepthRangeArrayvSamuel Pitoiset2017-07-313-1/+15
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add depth_range_arrayv() helperSamuel Pitoiset2017-07-311-6/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* dri_interface,egl,gallium: only expose RGBA visuals on AndroidMarek Olšák2017-07-312-3/+39
| | | | | | | | | | | | | | X/GLX can't handle them. This removes almost 500 GLX visuals that were incorrectly exposed. Add an optional getCapability callback for querying what the loader can do. I'm not splitting this patch, because it's already too small. v2: also add the callback to __DRIimageLoaderExtension Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 17.2 <[email protected]>
* radeonsi: expose MRT-draw-calls to HUDMarek Olšák2017-07-314-0/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: clamp viewport values only once when using glViewport()Samuel Pitoiset2017-07-311-12/+25
| | | | | | | | | | | It's useless to clamp the same values for all viewports. +7% in the "viewport change" test (drawoverhead benchmark). v2: - call clamp_viewport() in all callers of set_viewport_no_notify() Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* mesa: make _mesa_check_init_viewport() staticSamuel Pitoiset2017-07-312-8/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: Fix Thomas's email addressKenneth Graunke2017-07-283-3/+3
| | | | Commit 877128505431adaf817dc8069172ebe4a1cdf5d8 misspelled Hellstrom.
* i965: s/Tungsten Graphics/VMware/ in brw_bufmgr.c.Kenneth Graunke2017-07-281-3/+3
| | | | | | | | In commit 877128505431adaf817dc8069172ebe4a1cdf5d8, José replaced the Tungsten Graphics copyright notices with VMware, as Tungsten is gone. I later imported brw_bufmgr.c, reintroducing a Tungsten copyright. This commit does the equivalent of José's change to the new file.
* i965: Reformat the copyright header in brw_bufmgr.cKenneth Graunke2017-07-281-21/+18
| | | | | | | | | | | | | | This reformats the copyright header to match what we use in most of the newer parts of the driver. There are a few minor alterations: we change "COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS" to the standard "AUTHORS OR COPYRIGHT HOLDERS", and move the permission notice to the proper place (it should be in the middle, so "next paragraph" actually refers to something). Both of these changes match the OSI's MIT License text: https://opensource.org/licenses/MIT I copied this from genX_state_upload.c.
* radeonsi: update dirty_level_mask only when flushing or unbinding framebufferMarek Olšák2017-07-285-43/+59
| | | | | | | | | | | | | | This fixes corruption with bindless textures in Dawn Of War 3. The do_update_surf_dirtiness mechanism was complicated and dirty_level_mask was only updated after the first draw call. The problem is bindless textures are checked for decompression every draw call and we would only decompress after the first draw call. The solution is to set dirtiness after the last draw call to the framebuffer, so the (unconditional) decompression of bindless textures happens at the right time. Cc: 17.2 <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* Revert "drirc: whitelist glthread for Mount and Blade Warband"Marek Olšák2017-07-281-3/+0
| | | | | | | This reverts commit a7617a49fbde2fcfccdab22886aeabdbf8abb8e4. glthread disables itself automatically and therefore has no effect on the game.
* st/mesa: remove useless st_bufferobj_validate_usage()Samuel Pitoiset2017-07-282-19/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/mesa: remove st_cache.hSamuel Pitoiset2017-07-282-70/+0
| | | | | | | It contains unused prototypes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/glsl_to_tgsi: fix getting the image type for array of structsSamuel Pitoiset2017-07-281-1/+1
| | | | | | | | | | | | | | | | Since array splitting for AoA is disabled, we have to retrieve the type of the first non-array type when an array of images is declared inside a structure. Otherwise, it will hit an assert in glsl_type::sampler_index() because it expects either a sampler or an image type. This fixes a regression in the following piglit test: arb_bindless_texture/compiler/images/arrays-of-struct.frag Fixes: 57165f2ef8 ("glsl: disable array splitting for AoA") Cc: 17.2 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: fix mismatch when returning 64-bit bindless uniform handlesSamuel Pitoiset2017-07-281-1/+2
| | | | | | | | | | | | | The slower convert-and-copy process performs a bad conversion because it converts the value to signed 64-bit integer, but bindless uniform handles are considered unsigned 64-bit. This fixes "Check glUniform*() with mixed texture units/handles" from arb_bindless_texture-uniform piglit. Signed-off-by: Samuel Pitoiset <[email protected]> Cc: "17.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove gl_sync_object::Type fieldSamuel Pitoiset2017-07-282-5/+1
| | | | | | | This is useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: drop fence type parameter from NewSyncObject()Samuel Pitoiset2017-07-285-15/+9
| | | | | | | This is useless. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registersMarek Olšák2017-07-283-2/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rely on CLEAR_STATE for resetting the framebuffer and sample maskMarek Olšák2017-07-281-3/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use CLEAR_STATE to initialize some registersMarek Olšák2017-07-281-54/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: release sampler views when redefining a texture in st_context_teximageMarek Olšák2017-07-281-0/+2
| | | | | | | Noticed randomly. Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: for stencil only set Z tile mode index to same valueDave Airlie2017-07-281-0/+2
| | | | | | | | | | | | On SI this was causing a hang in dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint This was due to not handling the tile mode index for depth like I fixed previously for new GPUs. Fixes: 01d0c5a9 (radv: fix stencil regression since new addrlib import) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* virgl: drop precise modifier.Dave Airlie2017-07-281-0/+10
| | | | | | | | | The host doesn't understand this yet, so drop it for now. Fixes: virgl regressions. Fixes: af22adee4f (tgsi: add precise flag to tgsi_instruction) Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: always unconditionally revalidate main framebuffer after SwapBuffersMarek Olšák2017-07-281-0/+10
| | | | | | | | | This fixes the black Feral launcher window. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867 Cc: 17.2 <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* radeonsi: bail out instead of crashing if the main shader part failed to compileNicolai Hähnle2017-07-271-0/+3
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi: update a comment for merged shadersNicolai Hähnle2017-07-271-1/+5
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi/gfx9: dump previous stage LLVM IR for merged shadersNicolai Hähnle2017-07-271-0/+7
| | | | Reviewed: Marek Olšák <[email protected]>
* radeonsi: make sure TCS main output VGPRs don't alias inputsNicolai Hähnle2017-07-271-5/+13
| | | | | | | Avoids an unnecessary move introduce by "radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)" Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)Nicolai Hähnle2017-07-272-33/+79
| | | | | | | | | | | | | | | | | | With merged ESGS shaders, the GS part of a wave may be empty, and the hardware gets confused if any GS messages are sent from that wave. Since S_SENDMSG is executed even when EXEC = 0, we have to wrap even non-monolithic GS shaders in an if-block, so that the entire shader and hence the S_SENDMSG instructions are skipped in empty waves. This change is not required for TCS/HS, but applying it there as well simplifies the logic a bit. Fixes GL45-CTS.geometry_shader.rendering.rendering.* v2: ensure that the TCS epilog doesn't run for non-existing patches Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: fix vertex idx in ES with multiple waves per threadgroupNicolai Hähnle2017-07-271-1/+6
| | | | | Cc: [email protected] Reviewed: Marek Olšák <[email protected]>
* swr: fix transform feedback logicGeorge Kyriazis2017-07-274-8/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The shader that is used to copy vertex data out of the vs/gs shaders to the user-specified buffer (streamout or SO shader) was not using the correct offsets. Adjust the offsets that are used just for the SO shader: - Make sure that position is handled in the same special way as in the vs/gs shaders - Use the correct offset to be passed in the core - consolidate register slot mapping logic into one function, since it's been calculated in 2 different places (one for calcuating the slot mask, and one for the register offsets themselves Also make room for all attibutes in the backend vertex area. Fixes: - all vtk GL2PS tests - 18 piglit tests (16 ext_transform_feedback tests, arb-quads-follow-provoking-vertex and primitive-type gl_points v2: - take care of more SGV slots in slot mapping logic - trim feState.vsVertexSize - fix GS interface and incorporate GS while calculating vsVertexSize Note that vsVertexSize is used in the core as the one parameter that controls vertex size between all stages, so it has to be adjusted appropriately for the whole vs/gs/fs pipeline. Also note that GS and SO is not fully implemented. This will be addressed later. fixes: - fixes total of 20 piglit tests CC: 17.2 <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: non-regex knob fallback code for gcc < 4.9Tim Rowley2017-07-271-0/+21
| | | | | | | | gcc prior to 4.9 didn't implement <regex>, causing a startup crash in the swr knob parameter reading code. CC: <[email protected]> Reviewed-by: Bruce Cherniak <[email protected]>
* mesa: check that buffer object is not NULL before initializing itTimothy Arceri2017-07-271-4/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* glsl: small builtin inline tidy upTimothy Arceri2017-07-271-4/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* virgl: encode index buffer offset.Dave Airlie2017-07-271-1/+1
| | | | | | | Fixes arb_vertex_buffer_object-combined-vertex-index Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: Fix inversed test in st_api_destroy_drawableMichel Dänzer2017-07-271-1/+1
| | | | | | | | | | Fixes a drawable leak. Fixes: bbc29393d3be ("st/mesa: create framebuffer iface hash table per st manager") Bugzilla: https://bugs.freedesktop.org/101930 Tested-by: Nick Sarnie <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radv/ac: port SI TC L1 write corruption fix.Dave Airlie2017-07-261-3/+5
| | | | | | | | | This ports 72e46c988 to radv. radeonsi: apply a TC L1 write corruption workaround for SI Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/winsys: fix padding command stream for SIDave Airlie2017-07-261-4/+6
| | | | | | | | We were adding pad to size after creating the object, so we could submit a CS bigger than the bo created for it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: realign SI workaround with radeonsi.Dave Airlie2017-07-261-2/+3
| | | | | | | | | | | | This ports: da7453666ae radeonsi: don't apply the Z export bug workaround to Hainan to radv. Just noticed in passing. Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/clear: Don't perform redundant depth clearsJason Ekstrand2017-07-261-3/+31
| | | | | | | | | | | | | | | We already have this little optimization for color clears. Now that we're actually tracking whether or not a slice has any fast-clear blocks, it's easy enough to add for depth clears too. Improves performance of GFXBench 4 TRex at 1920x1080 by: - Skylake GT4: 0.905932% +/- 0.0620197% (n = 30) - Apollolake: 0.382434% +/- 0.1134730% (n = 25) v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're no longer necessary (other patches already landed to do that part) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Only do depth resolves prior to clearing when neededJason Ekstrand2017-07-261-3/+36
| | | | | | | | | | | | | | | | | | | When changing the clear value, we need to resolve any fast cleared data. Previously, we were performing resolves on every slice with HiZ enabled. We only need to resolve slices that a) have fast clear data, and b) aren't about to be cleared to the new color. In the latter case, we were actually doing a resolve, and then a fast clear - when we could skip both, causing the existing fast cleared area to be updated to the new clear value for no additional work. This patch stops using intel_miptree_prepare_access in favor of a more optimal open coded loop that knows about our clear operation. v2: (by Ken) Rebase on islification, write a real commit message. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.Kenneth Graunke2017-07-262-5/+8
| | | | | | I want to use it in brw_clear.c. Reviewed-by: Lionel Landwerlin <[email protected]>
* ac/surface: fix hybrid graphics where APU=GFX9, dGPU=olderMarek Olšák2017-07-261-0/+12
| | | | | | | | v2: don't do it for compressed textures (bpp = 0) Cc: 17.2 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
* radeonsi: decrease the number of compiler threadsMarek Olšák2017-07-262-3/+8
| | | | | Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: make S_FIXED function signed and move it to shared codeMarek Olšák2017-07-263-9/+5
| | | | | | | | | | | This fixes a bug uncovered by: 2412c4c81ea0488df865817a0de91ec46e359b72 util: Make CLAMP turn NaN into MIN. Cc: 17.2 <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: also clamp and quantize per-unit lod biasMarek Olšák2017-07-263-4/+6
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: fix unconditional return in st_framebuffer_iface_removeMarek Olšák2017-07-261-1/+1
| | | | | | | Noticed by James Legg @ Feral. Cc: 17.2 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
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