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* r300g: Be more verbose in what's killing us WRT vert formats.Corbin Simpson2009-11-071-4/+12
* r300g: Comments.Corbin Simpson2009-11-072-6/+11
* r300g: Don't assert on oversized VBOs, just return FALSE.Corbin Simpson2009-11-071-4/+12
* r300g: Moar vbo cleanup.Corbin Simpson2009-11-071-8/+12
* r300g: s/false/FALSE/Corbin Simpson2009-11-072-9/+9
* r300g: Clean up indexbuf render, switch to RELOC macro.Corbin Simpson2009-11-071-15/+17
* r300g: Clean up r300_setup_vertex_buffers.Corbin Simpson2009-11-071-15/+13
* r300g: Don't pass hw_prim around in the context.Corbin Simpson2009-11-075-81/+74
* r300g: Use common state funcs for translating vert formats.Corbin Simpson2009-11-071-72/+6
* r300g: don't hang GPU on misbehaving appsMaciej Cencora2009-11-071-0/+6
* r300g: VBOs WIPMaciej Cencora2009-11-0710-109/+477
* r300g: add missing flushMaciej Cencora2009-11-071-0/+2
* r300g: enable CS dumpingMaciej Cencora2009-11-071-2/+2
* r300g: move vborender context function to seperate fileMaciej Cencora2009-11-072-1/+6
* mesa: move code after declbrian2009-11-071-1/+2
* nv50: enable all 32 threads of a warpChristoph Bumiller2009-11-071-1/+3
* i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-063-17/+29
* i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-063-60/+72
* i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-064-127/+40
* i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-297/+109
* i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-221/+111
* i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-74/+29
* i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
* i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
* i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
* i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
* i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
* i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
* st/xorg: implement batching for the composite opZack Rusin2009-11-064-90/+161
* st/xorg: batch solid fill requestsZack Rusin2009-11-064-95/+66
* st/xorg: start accumulating vertices in a common bufferZack Rusin2009-11-062-48/+88
* st/xorg: use quads instead of triangle fansZack Rusin2009-11-061-4/+4
* st/xorg: make the buffer size globalZack Rusin2009-11-061-1/+9
* mesa: Reduce the source channels considered in optimization passes.Eric Anholt2009-11-061-1/+40
* mesa: Fix remove_instructions to successfully remove when removeFlags[0].Eric Anholt2009-11-061-0/+6
* mesa: Add an optimization path to remove use of pointless MOVs.Eric Anholt2009-11-061-1/+83
* mesa: Fix up the remove_dead_code pass to operate on a channel basis.Eric Anholt2009-11-061-28/+56
* intel: better front color buffer test in intelClear()Brian Paul2009-11-061-2/+3
* i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
* intel: Finish removing the fallback code for bug #16697.Eric Anholt2009-11-061-6/+2
* intel: Don't validate in a texture image used as a render target.Eric Anholt2009-11-063-11/+15
* mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture()Eric Anholt2009-11-061-0/+4
* intel: Clean up some extra struct indirection in finalize.Eric Anholt2009-11-061-2/+1
* intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt2009-11-061-4/+4
* intel: Remove duplicated arguments from intel_miptree_match_image().Eric Anholt2009-11-063-10/+7
* i965: Remove an XXX comment for testing some code that seems to work.Eric Anholt2009-11-061-1/+0
* intel: Remove obsolete comment about GEM in the spans code.Eric Anholt2009-11-061-1/+0
* intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt2009-11-067-51/+37
* Make a convenient int for what chipset generation we're on.Eric Anholt2009-11-065-9/+20
* Merge branch 'mesa_7_6_branch'Ian Romanick2009-11-068-570/+508
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