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* glsl: Drop exec_list argument to lower_ubo_referenceKristian Høgsberg Kristensen2015-11-104-5/+5
| | | | | | | | | | | We always pass in shader->ir and we already pass in the shader, so just drop the exec_list. Most passes either take just a exec_list or a shader, so this seems more consistent. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* nir/glsl: switch to using the builderConnor Abbott2015-11-101-441/+259
| | | | | | | v2: use nir_bulder_cf_insert (Ken) Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/glsl: make emit() take nir_ssa_def * sourcesConnor Abbott2015-11-101-18/+18
| | | | | | | Again, this matches what the builder will have to do. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/glsl: convert nir_visitor::result to a nir_ssa_def *Connor Abbott2015-11-101-6/+7
| | | | | | | | Its only user now returns a nir_ssa_def *, and we'll need this since the builder returns a nir_ssa_def *. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/glsl: make evaluate_rvalue() return a nir_ssa_def *Connor Abbott2015-11-101-37/+53
| | | | | | | | | | | A long time ago, before NIR was even merged to master, glsl_to_nir used registers and these sources were actually register sources. But nowadays everything in glsl_to_nir is an SSA value, so stop pretending that by evaluating an rvalue we can get an arbitrary nir_src. Most importantly, we need this since the builder takes nir_ssa_def * sources directly. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: Destroy buffer object's mutex.Jose Fonseca2015-11-101-0/+1
| | | | | | | | Ideally we should have a _mesa_cleanup_buffer_object function in src/mesa/bufferobj.c so that the destruction logic resided in a single place. Reviewed-by: Brian Paul <[email protected]>
* nir: Store PatchInputsRead and PatchOutputsWritten in nir_shader_info.Kenneth Graunke2015-11-102-0/+7
| | | | | | | | | | These tessellation shader related fields need plumbing through NIR. v2: Use uint32_t instead of uint64_t to match the source type of GLbitfield (caught by Iago Toral). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* vc4: Avoid loading undefined (newly-allocated) FBO contents.Eric Anholt2015-11-091-0/+17
| | | | | | | Since X has undefined contents in new pixmaps, it will allocate new textures for an FBO and draw to them without an explicit clear. For VC4, it's much faster to emit a clear than the load of the actual undefined memory contents, so just do that instead.
* vc4: Return NULL when we can't make our shadow for a sampler view.Eric Anholt2015-11-091-0/+4
| | | | | | | I'm not sure what the caller does is appropriate (just have a NULL sampler at this slot), but it fixes the immediate crash. Cc: "11.0" <[email protected]>
* vc4: Return GL_OUT_OF_MEMORY when buffer allocation fails.Eric Anholt2015-11-092-19/+32
| | | | | | | I was afraid our callers weren't prepared for this, but it looks like at least for resource creation, mesa/st throws an error appropriately. Cc: "11.0" <[email protected]>
* vc4: Add CL dumping for GL_ARRAY_PRIMITIVE.Eric Anholt2015-11-091-1/+16
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* vc4: Fix a compiler warning.Eric Anholt2015-11-091-1/+1
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* glsl: Use shared storage variable type for shared variablesJordan Justen2015-11-091-0/+2
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: Add shared variable typeJordan Justen2015-11-092-1/+2
| | | | | | | | | | Shared variables are stored in a common pool accessible by all threads in a compute shader local work group. These variables are similar to OpenCL's local/__local variables. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: Add space to shader_storage in print_visitorJordan Justen2015-11-091-1/+1
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: Align comments on variables typesJordan Justen2015-11-091-7/+7
| | | | | | | | v2: * Split from patch to add ir_var_shader_shared (tarceri) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: Parse shared keyword for compute shader variablesJordan Justen2015-11-095-1/+17
| | | | | | | | | | v2: * Move shared parsing under storage qualifiers (tarceri) * Fail to compile if shared is used in non-compute shader (tarceri) * Use separate shared_storage bit for shared variables (tarceri) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* glsl: simplify interface block stream qualifier validationTimothy Arceri2015-11-102-23/+14
| | | | | | | | | Qualifiers on member variables are redundent all we need to do if check if it matches the stream associated with the block and throw an error if its not. Reviewed-by: Samuel Iglesias Gonsalvez <[email protected]> Cc: Emil Velikov <[email protected]>
* st/wgl: add null pointer check for HUD textureBrian Paul2015-11-091-1/+3
| | | | | | Fixes crash when using HUD with Nobel Clinician Viewer. Reviewed-by: Jose Fonseca <[email protected]>
* st/wgl: fix double-present on swapbuffers bugBrian Paul2015-11-093-20/+12
| | | | | | | | | | | | | | | | | | The stw_st_framebuffer_present_locked() function was getting called twice per SwapBuffers. First, when st_context_iface::flush() was called from DrvSwapBuffers() because the ST_FLUSH_FRONT flag was given. Second, by stw_st_swap_framebuffer_locked() which does the actual SwapBuffers. Two code changes: 1. Pass ST_FLUSH_END_OF_FRAME, instead of ST_FLUSH_FRONT. 2. Move the implementation of stw_flush_current_locked() into DrvSwapBuffers() since it's not called anywhere else. Not much change in perf for benchmarks like Lightsmark, but some simple Mesa demos are measurably faster. Reviewed-by: José Fonseca <[email protected]>
* st/wgl: reorder pixel formats to put MSAA formats lastBrian Paul2015-11-091-29/+32
| | | | | | | | | | | | | And put 8-bit/channel formats before 5/6/5 formats. The ChoosePixelFormat() function seems to be finicky about format selection. Putting the MSAA formats after the non-MSAA formats means most apps get a low-numbered format. Now we generally get the same pixel format regardless of whether using vgpu9 or 10. VMware bug 1455030 Reviewed-by: José Fonseca <[email protected]>
* st/wgl: Don't rely on GDI to bookkeep pixelformat for us.José Fonseca2015-11-092-7/+6
| | | | | | | This allows to use apitrace's retracediff script on Windows to retrace and compare two builds of a Mesa based opengl32.dll/ICD side-by-side. See also https://github.com/apitrace/apitrace/commit/e4a4f15f5b92e0abbd24d7d053da25f8278c9f64
* winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3Michel Dänzer2015-11-091-11/+19
| | | | | | | | | | | | | | | Fixes GPUVM conflicts with non-4K page size. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92738 v2: Replace sanitization of VM base address alignment with comment why that's not necessary. v3: Use unsigned instead of long as the type for the size_align member. (Marek) Cc: [email protected] Reviewed-by: Christian König <[email protected]> (v1) Reviewed-by: Marek Olšák <[email protected]>
* st/omx: add headless supportLeo Liu2015-11-081-10/+35
| | | | | | | | | | | This will allow dec/enc/transcode without X v2: use env override even with X, use loader_open_device instead of open v3: clean up Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: use vl screen drm support from vl_wys_drmLeo Liu2015-11-081-21/+3
| | | | | | | v2: move the dup to vl_wys_drm for pipe loader Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: add drm support for vl_screenLeo Liu2015-11-083-1/+85
| | | | | | | | | | This will allow the state trackers to use render nodes with screen creation v2: dup fd for pipe loader Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: fix build fails with pipe loaderLeo Liu2015-11-081-2/+3
| | | | | | | There is no dev in drv, and dev should be from vl_screen here Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* nvc0: enable compute support on FermiSamuel Pitoiset2015-11-081-2/+2
| | | | | | | | | | | Altough the compute support is still not complete because textures and surfaces need to be implemented, it allows to launch very simple compute kernel like one which reads reading MP performance counters. This turns on PIPE_CAP_COMPUTE and PIPE_SHADER_COMPUTE. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix emission of s[] args in certain situationsIlia Mirkin2015-11-071-2/+2
| | | | | | | | | | There might only be a single arg (e.g. cvt), so use mode rather than looking at the source directly. Also we don't want to rely on the type of the value, which can be unreliable, but instead use the instruction's. This works out well since mkSplit doesn't adjust the type. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only take abs value when computing high resultIlia Mirkin2015-11-071-1/+1
| | | | | | | | Not reachable from TGSI since it only has UMUL, no IMUL. However it's surprising that setting argument types to s32 will cause sign to get lost. Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau: avoid queueing too much work onto a single fenceIlia Mirkin2015-11-072-26/+43
| | | | | | | | | | Force the fence to get kicked off, which won't actually wait for its completion, but any additional work will be put onto a fresh list. This fixes crashes in teximage-colors --benchmark with too many active maps. Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: disable front updates for nowDave Airlie2015-11-081-1/+1
| | | | | | | | As pointed out by Emil, this sometimes hangs, appears to be due to threading need to rethink how this stuff works for llvmpipe. Signed-off-by: Dave Airlie <[email protected]>
* virgl: wrap ret assignment with braces to do correct thingDave Airlie2015-11-082-2/+2
| | | | | | | Coverity reported that ret could only be 0 or 1, since it was setting ret = fn() > 0, instead of doing (ret = fn()) > 0. Signed-off-by: Dave Airlie <[email protected]>
* nir: Add a nir_deref_tail helperJason Ekstrand2015-11-073-23/+13
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/types: Add an is_vector_or_scalar helperJason Ekstrand2015-11-072-0/+7
| | | | Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: Use regs_read/written for post-RA scheduling in calculate_depsJason Ekstrand2015-11-071-11/+4
| | | | | | | | | | | | Previously, we were assuming that everything read/wrote exactly 1 logical GRF (1 in SIMD8 and 2 in SIMD16). This isn't actually true. In particular, the PLN instruction reads 2 logical registers in one of the components. This commit changes post-RA scheduling to use regs_read and regs_written instead so that we add enough dependencies. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92770 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir/validate: Add better validation of load/store typesJason Ekstrand2015-11-071-2/+14
| | | | Reviewed-by: Connor Abbott <[email protected]>
* radeonsi: add register definitions for StoneyMarek Olšák2015-11-071-0/+322
| | | | | | There are a few non-stoney changes too. Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: add workarounds for CP DMA to stay on the fast pathMarek Olšák2015-11-071-5/+88
| | | | | | v2: set emit_scratch_reloc, add a NULL check Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: unify CP DMA preparation logicMarek Olšák2015-11-071-37/+34
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: unify CP DMA code determining various flagsMarek Olšák2015-11-071-28/+23
| | | | | | v2: don't call get_flush_flags twice per function Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only enable write confirmation on the last CP DMA packetMarek Olšák2015-11-071-2/+4
| | | | | | This should improve performance for big copies that need to be split. Reviewed-by: Michel Dänzer <[email protected]>
* nv50/ir: allow emission of immediates in imul/imad opsIlia Mirkin2015-11-071-2/+8
| | | | | | | Nothing actually uses this yet (due to complications), but the emission logic is right. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: properly set the type of the constant folding resultIlia Mirkin2015-11-061-4/+4
| | | | | | | This removes the hack used for merge, which only covers a fraction of the cases. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for const-folding OP_CVT with F64 source/destIlia Mirkin2015-11-063-0/+45
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add fp64 opcode emission support for G200 (NVA0)Ilia Mirkin2015-11-061-10/+84
| | | | | | Need to emulate rcp/rsq before providing full fp64 support Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add support for 64bit immediates to checkSwapSrc01Hans de Goede2015-11-061-5/+6
| | | | | | | | Now that we support 64 bit immediates in insnCanLoad, we need to swap 64 bit immediate sources too for optimal effect. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: Teach insnCanLoad about double immediatesHans de Goede2015-11-061-6/+19
| | | | | | | | | | | | | | | | Teach insnCanLoad about double immediates, together with the "Add support for merge-s to the ConstantFolding pass" This turns the following (nvc0) code: 1: mov u32 $r2 0x00000000 (8) 2: mov u32 $r3 0x3fe00000 (8) 3: add f64 $r0d $r0d $r2d (8) Into: 1: add f64 $r0d $r0d 0.500000 (8) Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: Add support for merge-s to the ConstantFolding passHans de Goede2015-11-061-0/+15
| | | | | | | | | | | This allows later passes like LoadPropagation to properly deal with 64 bit immediates. If the new 64 bit load this introduces does not get optimized away then split64BitOpPostRA() will split this into 2 instructions again. Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: disallow 64-bit immediates on nv50 targetsIlia Mirkin2015-11-061-1/+1
| | | | | | No instructions are able to load short immediates like nvc0 can. Signed-off-by: Ilia Mirkin <[email protected]>
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