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* ilo: embed ilo_state_sbe in ilo_shaderChia-I Wu2015-06-1511-254/+169
* ilo: embed ilo_state_vf in ilo_ve_stateChia-I Wu2015-06-1512-330/+146
* ilo: embed ilo_state_urb in ilo_state_vectorChia-I Wu2015-06-159-350/+185
* ilo: embed ilo_state_sol in ilo_shaderChia-I Wu2015-06-158-151/+154
* ilo: embed ilo_state_cc in ilo_blend_stateChia-I Wu2015-06-1513-979/+462
* ilo: embed ilo_state_raster in ilo_rasterizer_stateChia-I Wu2015-06-1512-1186/+457
* ilo: embed ilo_state_viewport in ilo_viewport_stateChia-I Wu2015-06-1512-369/+142
* ilo: replace ilo_sampler_cso with ilo_state_samplerChia-I Wu2015-06-156-590/+258
* ilo: replace ilo_view_surface with ilo_state_surfaceChia-I Wu2015-06-159-1035/+205
* ilo: replace ilo_zs_surface with ilo_state_zsChia-I Wu2015-06-158-479/+105
* ilo: add ilo_state_psChia-I Wu2015-06-153-0/+848
* ilo: add ilo_state_{vs,hs,ds,gs}Chia-I Wu2015-06-153-0/+919
* ilo: add ilo_state_sbeChia-I Wu2015-06-153-0/+455
* ilo: add ilo_state_vfChia-I Wu2015-06-153-0/+637
* ilo: add ilo_state_urbChia-I Wu2015-06-153-0/+874
* ilo: add ilo_state_solChia-I Wu2015-06-153-0/+448
* ilo: add ilo_state_ccChia-I Wu2015-06-153-0/+1091
* ilo: add ilo_state_rasterChia-I Wu2015-06-153-0/+1262
* ilo: add ilo_state_viewportChia-I Wu2015-06-143-0/+512
* ilo: add ilo_state_samplerChia-I Wu2015-06-143-0/+847
* ilo: add ilo_state_surfaceChia-I Wu2015-06-143-0/+1297
* ilo: add ilo_state_zsChia-I Wu2015-06-143-0/+822
* ilo: update genhw headersChia-I Wu2015-06-1411-282/+298
* ilo: add ilo_image_disable_aux()Chia-I Wu2015-06-143-8/+28
* ilo: add array_size and level_count to ilo_imageChia-I Wu2015-06-142-0/+6
* ilo: add pipe_texture_target to ilo_imageChia-I Wu2015-06-146-23/+18
* ilo: fix "Render Cache Read Write Mode"Chia-I Wu2015-06-145-28/+12
* ilo: avoid resource owning in coreChia-I Wu2015-06-147-142/+27
* ilo: assert core objects are zero-initializedChia-I Wu2015-06-146-2/+29
* radeon/llvm: Handle LLVM backend rename from R600 to AMDGPUTom Stellard2015-06-121-0/+8
* gallivm: Only build lp_profile() body when PROFILE is definedTom Stellard2015-06-121-1/+1
* glsl: fix compile error messageTimothy Arceri2015-06-131-1/+1
* i965/gen8+: Add aux buffer alignment assertionsBen Widawsky2015-06-121-0/+22
* i965/gen9: Set HALIGN_16 for all aux buffersBen Widawsky2015-06-121-3/+19
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-123-7/+22
* i965: Extract tiling from fast clear decisionBen Widawsky2015-06-122-16/+30
* i965/gen9: Only allow Y-Tiled MCS buffersBen Widawsky2015-06-121-0/+2
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-129-75/+77
* glsl: enforce restriction on AoA interface blocks in GLSL ES 3.10Timothy Arceri2015-06-131-0/+11
* glsl: enforce fragment shader input restrictions in GLSL ES 3.10Timothy Arceri2015-06-131-0/+45
* glsl: enforce output variable rules for GLSL ES 3.10Timothy Arceri2015-06-131-0/+49
* i965/nir: Support barrier intrinsic functionJordan Justen2015-06-121-0/+4
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-125-0/+45
* i965: Add brw_barrier to emit a Gateway Barrier SENDJordan Justen2015-06-122-0/+32
* i965: Add brw_WAIT to emit wait instructionJordan Justen2015-06-122-0/+23
* i965: Add notification registerJordan Justen2015-06-121-0/+16
* i965: Disassemble Gateway SEND messagesJordan Justen2015-06-121-0/+16
* i965/inst: Add gateway_notify and gateway_subfuncid fieldsJordan Justen2015-06-121-3/+11
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
* nir: Add barrier intrinsic functionJordan Justen2015-06-122-1/+4
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