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* r300: Fixed a printf conversion warning.Oliver McFadden2007-03-151-2/+2
* r300: Fixed "no previous prototype for 'r300RefillCurrentDmaRegion'" warning.Oliver McFadden2007-03-151-2/+2
* added SWIZZLE_XXXX, YYYY, etc. macrosBrian2007-03-152-4/+11
* Committed Rune Petersen's fragment.position patch (Bug #10024) plus a few smallOliver McFadden2007-03-154-70/+103
* no-op clear if buffer width or height is zero (bug 7205)Brian2007-03-151-0/+3
* add some rb->Data null ptr checks (bug 7205)Brian2007-03-153-3/+5
* Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesaBrian2007-03-151-1/+1
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| * Fix off by one error in immediate state packet size.Keith Whitwell2007-03-151-1/+1
* | implement byteswapping for all multi-byte types in _mesa_pack_rgba_span_float...Brian2007-03-151-20/+17
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* pixelmap code simplificationBrian2007-03-141-253/+124
* Re-org of gl_pixel_attrib struct.Brian2007-03-145-203/+228
* clear the b->frontxrb->drawable field in xmesa_free_buffer(), see bug 7205Brian2007-03-141-0/+6
* Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesaBrian2007-03-1418-38/+151
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| * sync up t_vp_build.c brw_vs_tnl.c a bitRoland Scheidegger2007-03-132-20/+19
| * enable ARB_vertex_buffer_object for more dri driversRoland Scheidegger2007-03-138-0/+16
| * r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden2007-03-134-11/+11
| * use movdqu instead of movdqa for unaligned load avoiding a segfault (bug 10265)Roland Scheidegger2007-03-131-1/+1
| * Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden2007-03-133-3/+5
| * Documented the value written for R300_TX_CNTL cache flush.Oliver McFadden2007-03-132-1/+3
| * mesa: _mesa_unpack_imageXiang, Haihao2007-03-131-3/+89
| * Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to eitherOliver McFadden2007-03-133-4/+4
| * Guess another unknown register used for R300 pacification.Oliver McFadden2007-03-133-3/+7
| * i915tex: Don't crash when intel_fb->color_rb[i] is NULL.Michel Dänzer2007-03-121-1/+5
* | move CLIENT_ID code in xmesa_delete_framebuffer(), see bug 7205Brian2007-03-141-6/+3
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* clean-up, simplify _mesa_image_row_stride()Brian2007-03-121-23/+19
* take GL_UNPACK_ALIGNMENT into account in _mesa_image_row_stride() for GL_BITM...Brian2007-03-121-1/+6
* r200: Simplify r200SetCliprects like radeonSetCliprects in radeon and r300.Alan Swanson2007-03-124-22/+22
* r200: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-3/+6
* radeon: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-5/+8
* fix for bug#10196Xiang, Haihao2007-03-112-2/+16
* Guess another unknown register in R300 command buffer initialization. (Oliver...Aapo Tahkola2007-03-114-5/+6
* Renamed some of the unkXXX variables in the command buffer initOliver McFadden2007-03-113-72/+73
* Fix TEXREL issues.Brian2007-03-102-5/+122
* check for EXT_blend_equation_separate for 2.0Brian2007-03-101-1/+2
* i915tex: Fix build against libdrm git...Michel Dänzer2007-03-102-2/+3
* i915tex: Fix intel_wait_flips being declared implicitly.Michel Dänzer2007-03-101-0/+1
* i915tex: Fix build against released version of libdrm.Michel Dänzer2007-03-101-0/+17
* nouveau: fix nv04 swtcl.Stephane Marchesin2007-03-101-0/+1
* nouveau: fix the nv04 swtcl code.Stephane Marchesin2007-03-101-1/+1
* nouveau: oops don't debug by default.Stephane Marchesin2007-03-101-1/+1
* nouveau: some fixes to the nv04 state code.Stephane Marchesin2007-03-101-13/+15
* nouveau: add a fifo size debug check.Stephane Marchesin2007-03-102-3/+23
* Merge branch 'i915tex-pageflip'Michel Dänzer2007-03-1012-304/+608
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| * i915tex: Wait for pending scheduled flips before switching vsync pipe.Michel Dänzer2007-03-091-0/+19
| * i915tex: Set intel_fb->vbl_waited to current instead of what we aimed for.Michel Dänzer2007-03-091-1/+1
| * i915tex: Sync pages between pipes immediately again.Michel Dänzer2007-03-091-2/+12
| * i915tex: Do not wait for pending flips on both pipes at the same time.Michel Dänzer2007-03-091-9/+4
| * i915tex: Set framebuffer size to match window before calling _mesa_make_current.Michel Dänzer2007-03-071-10/+10
| * i915tex: Sync pages differently when crossing pipe borders.Michel Dänzer2007-02-281-12/+18
| * i915tex: Check that intel_rb is valid before trying to add it to an fbo.Michel Dänzer2007-02-281-2/+4
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