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* radeonsi: completely rework updating descriptors without CP DMAMarek Olšák2015-07-314-271/+128
| | | | | | | | | | | | | | | | | | | | The patch has a better explanation. Just a summary here: - The CPU always uploads a whole descriptor array to previously-unused memory. - CP DMA isn't used. - No caches need to be flushed. - All descriptors are always up-to-date in memory even after a hang, because CP DMA doesn't serve as a middle man to update them. This should bring: - better hang recovery (descriptors are always up-to-date) - better GPU performance (no KCACHE and TC flushes) - worse CPU performance for partial updates (only whole arrays are uploaded) - less used IB space (no CP_DMA and WRITE_DATA packets) - simpler code - hopefully, some of the corruption issues with SI cards will go away. If not, we'll know the issue is not here. Reviewed-by: Michel Dänzer <[email protected]>
* i965/fs: Fix regression with SIMD8 VS since ↵Francisco Jerez2015-07-311-1/+2
| | | | | | | | | | | | | | b5f1a48e234d47b24df38cb562cffb8941d43795. With num_direct_uniforms == 0 there's no space allocated in the param_size array for the one block of direct uniforms -- On the FS stage this would be a harmless no-op because it would simply re-set one of the param_size entries allocated for the sampler units to zero, but on the VS stage it has been reported to cause memory corruption followed by a crash -- Surprising how a full piglit run on Gen8 didn't catch it. Reported-and-reviewed-by: "Lofstedt, Marta" <[email protected]>
* i965/gen9: Add hs, ds, and cs thread + urb infoBen Widawsky2015-07-301-0/+10
| | | | | | | | | | | | | | | | | For SKL: These are the production values. For BXT: These are low estimates to enable platforms. This patch was originally part of i965/skl: Add production thread counts and URB size but was split out at Jordan's request (which I found to be reasonable). Note on stable inclusion: 10.6 does not care about hs, and ds. It does care about cs, but since Jordan was the one that asked me to extract it, I'll leave it up to him to deal with a backport to stable is required. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/bxt: Use more conservative thread countsBen Widawsky2015-07-301-2/+4
| | | | | | | | | | | | Since we really do not know what may occur in the future, pick a more conservative value for thread counts until we know better what values are correct. As far as I can tell, the old values will work fine, but some of the registers seem to indicate that going even lower is possible and the purpose of having early support is to enable as many configurations that can possibly exist (we can trim things down after platforms begin shipping later). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/skl: Add production thread counts and URB sizeBen Widawsky2015-07-301-5/+5
| | | | | | | | | | | | | This patch adjusts the SKL values to the best known values we have. v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the GEN9_FEATURES macro, however, doing that would require updating BXT values, and Jordan requested I not do that. Conveniently, this request makes a lot of sense wrt to stable backport as HS, and DS do not even exist there. Cc: [email protected] Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* vc4: Lower uniform loads to scalar in NIR.Eric Anholt2015-07-302-31/+81
| | | | | This also moves the vec4-to-byte-addressing math into NIR, so that algebraic has a chance at it.
* vc4: Move some FS input lowering into NIR.Eric Anholt2015-07-302-35/+50
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* vc4: Move program keys to the header file.Eric Anholt2015-07-302-47/+49
| | | | | I want to be able to inspect them from other files for lowering passes in NIR.
* vc4: Lower NIR inputs to scalar as well.Eric Anholt2015-07-302-4/+44
| | | | | For now this is just scalarizing, but it also means we'll get to dump a bunch of QIR-based lowering in a moment.
* vc4: Start adding a NIR-based output lowering pass.Eric Anholt2015-07-304-7/+137
| | | | | | For now, this just splits up store_output intrinsics to be scalars, and drops unused outputs in the coordinate shader. My goal is to be able to drop a bunch of my VC4-specific optimization by letting NIR handle it.
* vc4: Mark our shaders as single-threaded.Eric Anholt2015-07-302-0/+6
| | | | | I had my understanding of this bit flipped. We're using the full register space, so we need to say so.
* vc4: Avoid leaking indirect array access UBOs.Eric Anholt2015-07-301-0/+2
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* vc4: Avoid overflowing various static tables.Eric Anholt2015-07-304-4/+4
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* vc4: Fix return values from recent validation changes.Eric Anholt2015-07-301-4/+4
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* st/mesa: don't draw instead of asserting in transform feedbackDave Airlie2015-07-313-4/+7
| | | | | | | | | | | | if we get a request to take the count from feedback, but there is no buffer to take it from, just draw as if we got 0 vertices so nothing. This fixes this assert killing the ogl conform, and a piglit test I've sent. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: remove now unused _mesa_get_uniform_locationTimothy Arceri2015-07-302-79/+0
| | | | | Cc: Tapani Pälli <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: remove now unused subscript validationsTimothy Arceri2015-07-302-108/+0
| | | | | Cc: Tapani Pälli <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: fix and simplify resource query for arraysTimothy Arceri2015-07-305-92/+106
| | | | | | | | | | | | | | | | | | | | | | This removes the need for multiple functions designed to validate an array subscript and replaces them with a call to a single function. The change also means that validation is now only done once and the index is retrived at the same time, as a result the getUniformLocation code can be simplified saving an extra hash table lookup (and yet another validation call). This chage also fixes some tests in: ES31-CTS.program_interface_query.uniform V3: rebase on subroutines, and move the resource index array == 0 check into _mesa_GetProgramResourceIndex() to simplify things further V2: Fix bounds checks for program input/output, split unrelated comment fix and _mesa_get_uniform_location() removal into their own patch. Cc: Tapani Pälli <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/bxt: Don't use brw_device_info_skl_early on BXTNeil Roberts2015-07-301-1/+3
| | | | | | | | Previously it could end up using the “SKL early” device on BXT depending on the revision number. This would probably break things because for example has_llc would be wrong. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: set stage flag for structs and arrays in resource listTimothy Arceri2015-07-301-3/+13
| | | | | | | | This fixes the remaining failing tests in: ES31-CTS.program_interface_query.uniform-types Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* radeonsi: enable GL4.1 and update documentation (v2)Dave Airlie2015-07-301-1/+1
| | | | | | | | | | This enables GL4.1 for radeonsi, and updates the docs in the correct places. v2: enable only for llvm 3.7 which has fixes in place. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: add GS multiple streams support (v2)Dave Airlie2015-07-306-39/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the final piece for ARB_gpu_shader5, The code is based on the r600 code from Glenn Kennard, and myself. While developing this, I'm not 100% sure of all the calculations made in the GS registers, this is why the max_stream is worked out there and used to limit the changes in registers. Otherwise my initial attempts either regressed GS texelFetch tests or primitive-id-restart. The current code has no regressions in piglit. This commit doesn't enable ARB_gpu_shader5, since that just bumps the glsl level to 4.00, so I'll just do a separate patch for 4.10. v1.1: fix bug introduced in rebase. v2: Address Marek's review comments, remove my llvm stream code for simpler C, move gsvs_ring and gs_next_vertex to arrays. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Delete unused functions in format parserAnuj Phogat2015-07-291-7/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Change the type of max_{vs, hs, ...}_threads variables to unsignedAnuj Phogat2015-07-292-7/+7
| | | | | | | | | Fixes following compiler warning: brw_cs.cpp:386:27: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()Anuj Phogat2015-07-298-26/+15
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* gallium/auxiliary: Ensure c99_math.h is included.Jose Fonseca2015-07-291-1/+2
| | | | | | As it is needed for exp2. Trivial.
* i965/bxt: Support 3src simd16 instructionsBen Widawsky2015-07-291-3/+1
| | | | | | | | | This is easily accomplished by moving simd16 3src to GEN9_FEATURES. v2: small cleanup to make it more similar to GEN8_FEATURES Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* targets/dri: scons: add missing link against libdrmEmil Velikov2015-07-291-0/+2
| | | | | | | | | Otherwise the final dri module will have (additional) unresolved symbols. Cc: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviwed-by: Jose Fonseca <[email protected]>
* svga: scons: remove unused HAVE_SYS_TYPES_H defineEmil Velikov2015-07-292-2/+0
| | | | | | | | | There isn't a single instance in mesa that mentions HAVE_SYS_TYPES_H, other than this file. Cc: Jose Fonseca <[email protected]> Acked-by: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* glsl: Avoid double promotion.Matt Turner2015-07-291-2/+2
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* mesa: Avoid double promotion.Matt Turner2015-07-2914-49/+49
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa/math: Avoid double promotion.Matt Turner2015-07-293-46/+46
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* program: Avoid double promotion.Matt Turner2015-07-291-15/+15
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* swrast: Avoid double promotion.Matt Turner2015-07-2913-50/+50
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* tnl: Avoid double promotion.Matt Turner2015-07-297-30/+28
| | | | | | There are a couple of unrelated changes in t_vb_lighttmp.h that I hope you'll excuse -- there's a block of code that's duplicated modulo a few trivial differences that I took the liberty of fixing.
* vbo: Avoid double promotion.Matt Turner2015-07-292-5/+5
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* util: Avoid double promotion.Matt Turner2015-07-291-1/+1
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* gallium/auxiliary: Avoid double promotion.Matt Turner2015-07-292-2/+2
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Avoid double promotion.Matt Turner2015-07-291-2/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Use float calculations when double is unnecessary.Matt Turner2015-07-2914-34/+35
| | | | | | | | | | | | | | | | | Literals without an f/F suffix are of type double, and implicit conversion rules specify that the float in (float op double) be converted to a double before the operation is performed. I believe float execution was intended (in nearly all cases) or is sufficient (in the case of gen7_urb.c). Removes a lot of float <-> double conversion instructions and replaces many double instructions with float instructions which are cheaper. text data bss dec hex filename 4928659 195160 26192 5150011 4e953b i965_dri.so before 4928315 195152 26192 5149659 4e93db i965_dri.so after Reviewed-by: Iago Toral Quiroga <[email protected]>
* gallium/auxiliary: Use exp2(x) instead of pow(2.0, x).Matt Turner2015-07-292-4/+4
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* program: Use exp2(x) instead of pow(2.0, x).Matt Turner2015-07-291-2/+2
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* mesa: Use floats for viewport bounds.Matt Turner2015-07-2914-22/+22
| | | | | | | | | | | | | | | | | | ARB_viewport_array specifies that DEPTH_RANGE consists of double- precision parameters (corresponding commit d4dc35987), and a preparatory commit (6340e609a) added _mesa_get_viewport_xform() which returned double-precision scale[3] and translate[3] vectors, even though X, Y, Width, and Height were still floats. All users of _mesa_get_viewport_xform() immediately convert the double scale and translation vectors into floats (which were floats originally, but were converted to doubles in _mesa_get_viewport_xform(), sigh). i965 at least cannot consume doubles (see SF_CLIP_VIEWPORT). If we want to pass doubles to hardware, we should have a different function that does that. Acked-by: Mathias Froehlich <[email protected]>
* glsl: Remove MSVC implementations of copysign and isnormal.Matt Turner2015-07-292-26/+2
| | | | Non-Gallium parts of Mesa require MSVC 2013 which provides these.
* i965/fs: Make the default builder 64-wide before entering the optimization loop.Francisco Jerez2015-07-292-2/+7
| | | | | | | | | | | Not a typo. Replace the default builder with one of bogus width to catch cases in which optimization passes assume that the default dispatch width is good enough. The execution controls of instructions emitted during optimization should in general match the original code that is being manipulated. Many of the problems fixed in this series were caught by the assertions introduced in this patch. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Don't set exec_all on instructions wider than the original in ↵Francisco Jerez2015-07-291-9/+11
| | | | | | | | | | | | | lower_simd_width. This could have led to somewhat increased bandwidth usage for lowered texturing instructions on Gen4 (which is the only case in which lower_width may be greater than inst->exec_size). After the previous patches the invariant mentioned in the comment should no longer be assumed by any of the other optimization and lowering passes, so the exec_all() call shouldn't be necessary anymore. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Initialize a builder explicitly in the gen4 send dependency ↵Francisco Jerez2015-07-291-4/+7
| | | | | | | | | | | work-arounds. Instead of relying on the default one. This shouldn't lead to any functional changes because DEP_RESOLVE_MOV overrides the execution size of the instruction anyway and other execution controls are irrelevant. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cfg: Assert that cur_do/while/if pointers are non-NULL.Matt Turner2015-07-291-0/+3
| | | | More.. like in commit 4d93a07c.
* nvc0/ir: cache vertex out base so that we don't recompute againIlia Mirkin2015-07-291-8/+15
| | | | | | | | The global CSE pass stinks and is unable to pull this out. Easy enough to handle it here and avoid generating unnecessary special register loads (which can allegedly be quite slow). Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: output base for reading is based on laneidIlia Mirkin2015-07-291-0/+25
| | | | | | | | | | | PFETCH retrieves the address for incoming vertices, not output vertices in TCS. For output vertices, we must use the laneid as a base. Fixes barrier piglit test, which was failing for entirely non-barrier reasons, but rather that it was (a) trying to draw multiple patches and (b) the incoming patch size was not the same as the outgoing patch size. Signed-off-by: Ilia Mirkin <[email protected]>
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