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* mesa: use implementation specified MAX_VERTEX_ATTRIBS rather than hardcoded ↵Timothy Arceri2015-07-081-6/+2
| | | | | | value Reviewed-by: Ilia Mirkin <[email protected]>
* i965/vs: Fix matNxM vertex attributes where M != 4.Kenneth Graunke2015-07-071-4/+11
| | | | | | | | | | | | | Matrix vertex attributes have their columns padded out to vec4s, which I was failing to account for. Scalar NIR expects them to be packed, however. Fixes 1256 dEQP tests on Broadwell. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* st/dri: don't set PIPE_BIND_SCANOUT for MSAA surfacesMarek Olšák2015-07-071-1/+1
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91231 Reviewed-by: Brian Paul <[email protected]>
* gallium/hud: display percentages with % suffixBrian Paul2015-07-071-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: add PIPE_DRIVER_QUERY_TYPE_MICROSECONDS for HUDBrian Paul2015-07-072-10/+26
| | | | | | | | This allows drivers to report queries in units of microseconds and have the HUD display "us" (microseconds), "ms" (milliseconds) or "s" (seconds) on the graph. Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: replace byte units flag with pipe_driver_query_typeBrian Paul2015-07-073-16/+18
| | | | | | | Instead of using a boolean 'is bytes' value, use the pipe_driver_query_type enum type. This will let is add support for time values in the next patch. Reviewed-by: Marek Olšák <[email protected]>
* gallium/os: minor whitespace fixes in os_time.hBrian Paul2015-07-071-5/+6
| | | | Trivial.
* i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.Francisco Jerez2015-07-071-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was probably disabled due to a combination of several bugs in the generator code (fixed earlier in this series) and a misunderstanding of the hardware spec. The documentation for most control flow instructions mentions among other restrictions: "Instruction compression is not allowed." This however doesn't have any implications on 16 wide not being supported, because none of the control flow instructions have multi-register operands (control flow instructions are not compressed on more recent hardware either, except maybe SNB's IF with inline compare). In fact Gen4-5 had 16-wide control flow masks and stacks, and the spec mentions in several places that control flow instructions push and pop 16 channels worth of data -- Otherwise there doesn't seem to be any indication that it shouldn't work. Causes no piglit regressions, and gives the following shader-db results on ILK: total instructions in shared programs: 4711384 -> 4711384 (0.00%) instructions in affected programs: 0 -> 0 helped: 0 HURT: 0 GAINED: 1215 LOST: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.Francisco Jerez2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | From the hardware docs for the DO instruction: "Execution size is ignored for this instruction." My observation on ILK hardware contradicts the spec though, channels over the execution size of a DO instruction won't enter the loop, and channels over the execution size of a WHILE instruction will exit the loop after the first iteration -- The latter is consistent with the spec though, there's no claim about the execution size being ignored for the WHILE instruction so it's not completely unexpected that it has an influence on the evaluation of EMask. The execute_size argument of brw_DO() shouldn't have any effect on Gen6 and newer hardware. On Gen4-5 WHILE instructions inherit the execution size from the matching DO, so this patch should fix them too. The execution size of BREAK and CONT instructions was already being set correctly. Fixes some 50 piglit tests on Gen4-5 when forced to run shaders with conditional and loop instructions 16-wide, e.g. shaders/glsl-fs-continue-inside-do-while. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4-5: Set ENDIF dst and src0 fields to the null register.Francisco Jerez2015-07-071-2/+2
| | | | | | | | | | | | | | The hardware docs don't mention explicitly what these fields should be, but I've verified experimentally on ILK that using a GRF as destination causes the register to be corrupted when the execution size of an ENDIF instruction is higher than 8 -- and because the destination we were using was g0, eventually a hang. Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: Use param export count from si_llvm_export_vs in si_shader_vsMichel Dänzer2015-07-073-22/+6
| | | | | | | | | | | | This eliminates the error prone logic in si_shader_vs recalculating this value. It also fixes TGSI_SEMANTIC_CLIPDIST outputs incorrectly not being counted for VS exports. They need to be counted because they are passed to the pixel shader as parameters as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91193 Reviewed-by: Marek Olšák <[email protected]>
* mesa: Convert some asserts into STATIC_ASSERT.Matt Turner2015-07-061-7/+6
| | | | Reviewed-by: Chad Versace <[email protected]>
* gallivm: fix lp_build_compare_extRoland Scheidegger2015-07-062-1/+4
| | | | | | | | | | | | The expansion should always be to the same width as the input arguments no matter what, since these functions should work with any bit width of the arguments (the sext is a no-op on any sane simd architecture). Thus, fix the caller expecting differently. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=91222 Tested-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Add a MUST_CHECK macro for __attribute__((warn_unused_result)).Kenneth Graunke2015-07-061-0/+6
| | | | | | | | | In the kernel, this is called __must_check; all our attribute macros in Mesa appear to be uppercase, so I went with that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Make sure not to dereference NULLNeil Roberts2015-07-061-1/+1
| | | | | | | | | | In this bit of code point_five can be NULL if the expression is not a constant. This fixes it to match the pattern of the rest of the chunk of code so that it checks for NULLs. Cc: Matt Turner <[email protected]> Cc: "10.6" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Add missing check for whether an expression is an add operationNeil Roberts2015-07-061-1/+1
| | | | | | | | | | | | | | | There is a piece of code that is trying to match expressions of the form (mul (floor (add (abs x) 0.5) (sign x))). However the check for the add expression wasn't checking whether it had the expected operation. It looks like this was just an oversight because it doesn't match the pattern for the rest of the code snippet. The existing line to check whether add_expr!=NULL was added as part of a coverity fix in 3384179f. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91226 Cc: Matt Turner <[email protected]> Cc: "10.6" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Reserve more batch space to accomodate Gen6 perfmonitors.Kenneth Graunke2015-07-061-2/+2
| | | | | | | | | | | | | | | Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's actually 5 DWords on Gen6-7. We've been reserving insufficient space for performance monitoring on Sandybridge, which means it would likely break if you used that functionality. (Thankfully, no one does...) Also, the existing number of 146 was the result of me flubbing up the arithmetic: it should have actually been 140. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRANeil Roberts2015-07-064-0/+9
| | | | | | | | | | | On Gen9+ there is a new bit in 3DSTATE_PS_EXTRA that must be set if the shader sends a message to the pixel interpolator. This fixes the interpolateAt* tests on SKL, apart from interpolateatsample-nonconst but that is not implemented anywhere so it's not a regression. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.6 10.5" <[email protected]>
* winsys/radeon: use os_wait_until_zero in radeon_bo_set_tilingMarek Olšák2015-07-051-3/+1
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* radeonsi: don't flush an empty IB if the only thing we need is a fenceMarek Olšák2015-07-053-3/+15
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/os: add conversion and wait functions for absolute timeoutsMarek Olšák2015-07-052-0/+67
| | | | | | | | Absolute timeouts are used with the amdgpu kernel driver. It also makes waiting for several variables and fences at the same time easier (the timeout doesn't have to be recalculated after every wait call). Reviewed-by: Alex Deucher <[email protected]>
* gallium/os: add os_wait_until_zero (v2)Marek Olšák2015-07-052-1/+48
| | | | | | | | | | This will be used by radeon and amdgpu winsyses. Copied from the amdgpu winsys. v2: use volatile and p_atomic_read Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: mark the gpu load thread stop trigger as volatileMarek Olšák2015-07-051-1/+1
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* st/mesa: if a fence isn't returned, assume it's signalledMarek Olšák2015-07-051-1/+13
| | | | | The reason might be that no commands have been submitted before the flush and the GPU is idle.
* gallium: remove redundant pipe_context::fence_signalledMarek Olšák2015-07-0513-131/+0
| | | | | | fence_finish(timeout=0) does the same thing Reviewed-by: Brian Paul <[email protected]>
* gallium: use fence_finish instead of fence_signalled in state trackersMarek Olšák2015-07-055-5/+5
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium: handle fence_finish timeout in various driversMarek Olšák2015-07-055-0/+15
| | | | | | I copied what fence_signalled does. Reviewed-by: Brian Paul <[email protected]>
* gallium/docs: remove out-of-date document about D3D11 featuresMarek Olšák2015-07-051-462/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* radeonsi: fix a hang with DrawTransformFeedback on 4 SE chipsMarek Olšák2015-07-051-0/+4
| | | | | | Cc: 10.6 10.5 <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* glsl: update types for unsized arrays of membersTimothy Arceri2015-07-041-2/+16
| | | | | | | Assigns a new array type based on the max access of unsized array members. This is to support arrays of arrays. Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: update assert to support arrays of arraysTimothy Arceri2015-07-041-1/+2
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: allow precision qualifiers for AoATimothy Arceri2015-07-041-3/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: UCMP arguments are float, so make sure modifiers are appliedIlia Mirkin2015-07-031-1/+2
| | | | | | | | | The first argument to UCMP needs to be compared against 0, but the latter arguments are treated as float and need to be able to properly apply neg/abs arguments. Adjust the inferSrcType function accordingly. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* glsl: add a missing call to _mesa_locale_initErik Faye-Lund2015-07-032-3/+3
| | | | | | | | | | After c61bc6e ("util: port _mesa_strto[df] to C"), "make check" fails due to a missing _mesa_locale_init. Fixup this oversight, by moving the stand-alone compiler initializer inside initialize_context_to_defaults(). Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Erik Faye-Lund <[email protected]>
* winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.Mario Kleiner2015-07-031-3/+10
| | | | | | | | | | | | | | Same problem and fix as for nouveau's ZaphodHeads trouble. See patch ... "nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads." ... for reference. Cc: "10.3 10.4 10.5 10.6" <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: disable single-sample fast color clear due to hangsMarek Olšák2015-07-031-1/+6
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73528 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82186 Cc: 10.4 10.5 10.6 <[email protected]>
* r600g,radeonsi: implement get_device_reset_statusMarek Olšák2015-07-036-4/+38
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* dri/common: allow BGRX sRGB visualsMarek Olšák2015-07-031-0/+1
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* mesa: fix sRGB rendering for GLES1Marek Olšák2015-07-031-6/+4
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* egl: sort extension lists alphabeticallyMarek Olšák2015-07-033-54/+51
| | | | and add the missing KHR_gl_colorspace case.
* egl: implement EGL_KHR_gl_texture_3D_imageAnatoli Antonovitch2015-07-031-3/+17
| | | | Most of the code has been in place already.
* freedreno/ir3: don't be confused by eliminated indirectsRob Clark2015-07-032-0/+14
| | | | | | | | If an instruction using address register value gets eliminated, we need to remove it from the indirects list, otherwise it causes mayhem in sched for scheduling address register usage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sched fixes for addr register usageRob Clark2015-07-031-12/+65
| | | | | | | | | | | | | | | | A handful of fixes and cleanups: 1) If we split addr/pred, we need the newly created instruction to end up in the unscheduled_list 2) Avoid scheduling a write to the address register if there is no instruction using the address register that is otherwise ready to schedule. Note that I currently don't bother with the same logic for predicate register, since the only instructions using predicate (br/kill) don't take any other src registers, so this situation should not arise. 3) few other cosmetic cleanups Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix indirects trackingRob Clark2015-07-035-10/+23
| | | | | | | | | | cp would update instr->address but not update the indirects array resulting in sched getting confused when it had to 'spill' the address register. Add an ir3_instr_set_address() helper to set instr->address and also update ir->indirects, and update all places that were writing instr->address to use helper instead. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: mark location specially in nir for color0-writes-allIlia Mirkin2015-07-033-1/+16
| | | | | | | | | | We need to distinguish a shader that has separate writes to each MRT from one which is supposed to write the data from MRT 0 to all the MRTs. In TGSI this is done with a property. NIR doesn't have that, so encode it as a funny location and decode on the other end. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/lower_phis_to_scalar: undef is trivially scalarizableRob Clark2015-07-031-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* gallium/ttn: IN/OUT are only array if ArrayID != 0Rob Clark2015-07-031-62/+81
| | | | | | | | Fixes issue with gallium HUD. See this thread for details: http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* tgsi: update docs for ArrayID usageRob Clark2015-07-031-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Don't disable SIMD16 when using the pixel interpolatorNeil Roberts2015-07-031-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a comment saying that in SIMD16 mode the pixel interpolator returns coords interleaved 8 channels at a time and that this requires extra work to support. However, this interleaved format is exactly what the PLN instruction requires so I don't think anything needs to be done to support it apart from removing the line to disable it and to ensure that the message lengths for the send message are correct. I am more convinced that this is correct because as it says in the comment this interleaved output is identical to what is given in the thread payload. The code generated to apply the plane equation to these coordinates is identical on SIMD16 and SIMD8 except that the dispatch width is larger which implies no special unmangling is needed. Perhaps the confusion stems from the fact that the description of the PLN instruction in the IVB PRM seems to imply that the src1 inputs are not interleaved so it wouldn't work. However, in the HSW and BDW PRMs, the pseudo-code is different and looks like it expects the interleaved format. Mesa doesn't seem to generate different code on IVB to uninterleave the payload registers and everything is working so I can only assume that the PRM is wrong. I tested the interpolateAt tests on HSW and did a full Piglit run on IVB on there were no regressions. Reviewed-by: Chris Forbes <[email protected]>
* nir: Don't allow copying SSA destinationsJason Ekstrand2015-07-021-11/+11
| | | | Reviewed-by: Connor Abbott <[email protected]>
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