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* draw/gallivm: add invocation ID support for llvmpipe.Dave Airlie2015-06-235-3/+14
| | | | | | | This extends the draw code to add support for invocations. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* draw/tgsi: implement geom shader invocation support.Dave Airlie2015-06-234-18/+34
| | | | | | | | This is just for softpipe, llvmpipe won't work without some changes. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: handle indirect sampler arrays. (v2)Dave Airlie2015-06-231-4/+38
| | | | | | | | | This is required for ARB_gpu_shader5 support in softpipe. v2: add support to txd/txf/txq paths. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir: Allow vec2/vec3/vec4 instructions in the select peephole pass.Kenneth Graunke2015-06-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are basically just moves, so they should be safe as well. When disabling i965's GLSL IR level scalarizer (channel expressions) pass, I started seeing NIR code like this: if ssa_21 { block block_1: /* preds: block_0 */ vec4 ssa_120 = vec4 ssa_82, ssa_83, ssa_84, ssa_30 /* succs: block_3 */ } else { block block_2: /* preds: block_0 */ /* succs: block_3 */ } block block_3: /* preds: block_1 block_2 */ vec4 ssa_33 = phi block_1: ssa_120, block_2: ssa_2 Previously, the GLSL IR scalarizer pass would break the vec4 into a series of fmovs, which were allowed by the peephole pass. But with the vec4 operation, they were not. We want to keep getting selects. Normal i965 on Broadwell: instructions in affected programs: 200 -> 176 (-12.00%) helped: 4 With brw_fs_channel_expressions() disabled: instructions in affected programs: 1832 -> 1646 (-10.15%) helped: 30 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965: Add and fix comments in brw_vue_map.c.Kenneth Graunke2015-06-221-1/+13
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Split VUE map handling out of brw_vs.c into brw_vue_map.c.Kenneth Graunke2015-06-223-102/+137
| | | | | | | | | | | This was originally only used by the vertex shader, but it's now used by the geometry shader as well, and will also eventually be used for tessellation control and evaluation shaders. I suspect it will be easier to find in a file named after the concept. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Implement Push Constant Buffer workaroundBen Widawsky2015-06-221-7/+41
| | | | | | | | | | | | | | | | | | | | | | | This implements a workaround (exact excerpt as a comment in the code). The docs specify [clearly, after you struggle for a while] that the offset isn't relative to state base. This actually makes sense. This fixes hangs on SKL. Buffer #0 is meant to be used for normal uniforms. Buffer #1 is typically used for gather constants when using RS. Buffer #1-#3 could be used to push a bunch of UBO data which would just be somewhere in memory, and not relative to the dynamic state. NOTE: I've moved away from the ternary operator for the new gen9 conditions. Admittedly it's probably not great to do this, but I really want to fix this all up in the subsequent patch and doing it here makes that diff a lot nicer. I want to split out the gen8/9 code to make the function a bit more readable, but to keep this easily cherry-pickable I am doing this fix first. If we decide not to merge the cleanup patch then I can revisit this. Cc: "10.5 10.6" <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Tested-by: Valtteri Rantala <[email protected]>
* mesa: use _mesa_lookup_enum_by_nr() in print_array()Brian Paul2015-06-221-4/+4
| | | | | | Print GL_FLOAT, etc. instead of hex value. Reviewed-by: Ilia Mirkin <[email protected]>
* ilo: emit 3DPRIMITIVE from gen6_3dprimitive_infoChia-I Wu2015-06-2211-87/+91
| | | | | | It allows us to remove ilo_ib_state::draw_start_offset and ILO_PRIM_RECTANGLES. gen6_3d_translate_pipe_prim() is also replaced by ilo_translate_draw_mode().
* ilo: align vertex buffer size in buf_create()Chia-I Wu2015-06-222-19/+20
| | | | | With ilo_format.[ch] moved out of core, the aligning of vertex buffers does not belong to core anymore.
* ilo: move ilo_format.[ch] out of coreChia-I Wu2015-06-225-8/+8
| | | | | They provide PIPE_FORMAT_x to GEN6_FORMAT_x translation as well as some convenient helpers. Move them out of core.
* ilo: add ilo_state_surface_valid_format()Chia-I Wu2015-06-224-284/+364
| | | | Check if a surface format can be used for the specified access type.
* ilo: add ilo_state_vf_valid_element_format()Chia-I Wu2015-06-223-124/+132
| | | | Check if a surface format can be used as a VE format.
* nvc0: use NV_VRAM_DOMAIN() macroAlexandre Courbot2015-06-2211-22/+27
| | | | | | | | | Use the newly-introduced NV_VRAM_DOMAIN() macro to support alternative VRAM domains for chips that do not have dedicated video memory. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* nouveau: support for custom VRAM domainsAlexandre Courbot2015-06-222-0/+14
| | | | | | | | | | | | | | | | | | | | | Some GPUs (e.g. GK20A, GM20B) do not embed VRAM of their own and use the system memory as a backend instead. For such systems, allocating objects in VRAM results in errors since the kernel will not allow VRAM objects allocations. This patch adds a vram_domain member to struct nouveau_screen that can optionally be initialized to an alternative domain to use for VRAM allocations. If left untouched, NOUVEAU_BO_VRAM will be used for systems that embed VRAM, and NOUVEAU_BO_GART will be used for VRAM-less systems. Code that uses GPU objects is then expected to use the NV_VRAM_DOMAIN() macro in place of NOUVEAU_BO_VRAM to ensure correct behavior on VRAM-less chips. Signed-off-by: Alexandre Courbot <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* ilo: add ilo_state_computeChia-I Wu2015-06-228-92/+586
| | | | | Replace gen6_idrt_data with ilo_state_compute, which has a bunch of validations and is now preferred.
* r600g: ignore sampler views for now.Dave Airlie2015-06-221-0/+1
| | | | | | | This fixes a regression in that r600 stopped working when sampler views were pushed. Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: pass sz to split_dest()Rob Clark2015-06-212-5/+7
| | | | | | | | | | | | | | | | | | | | For query_levels, we generate a getinfo with writemask of (z), which RA will consider as size==3. But we were still generating four fanouts. Which meant that RA would see it as two different register classes, depending on the path to definer. Ie. on the getinfo instruction itself it would see size==3, but when chasing back through the fanouts it would see size==4. Easiest way to solve that is to just generate the chain of neighboring fanouts to have the correct size in the first place. Note: we may eventually want split_dest() to take start/end or wrmask instead, since really we only need size==1. But RA is not clever enough for that, query_levels is not that common, and the other two registers that get allocated are never used so those register slots can be immediately re-used. So bunch of work for probably no real gain. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: add more opcodesRob Clark2015-06-211-1/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: only unminify txf coords on a3xxRob Clark2015-06-211-1/+9
| | | | | | Seems like a4xx gets this right. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove int sampler shader variantsRob Clark2015-06-218-104/+7
| | | | | | | | We get this information from NIR (which gets it from sview decl in tgsi when translating from tgsi), so no need to maintain shader variants for this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: block reshuffling and loops!Rob Clark2015-06-2110-126/+1025
| | | | | | | | | | | | | | | | This shuffles things around to allow the shader to have multiple basic blocks. We drop the entire CFG structure from nir and just preserve the blocks. At scheduling we know whether to schedule conditional branches or unconditional jumps at the end of the block based on the # of block successors. (Dropping jumps to the following instruction, etc.) One slight complication is that variables (load_var/store_var, ie. arrays) are not in SSA form, so we have to figure out where to put the phi's ourself. For this, we use the predecessor set information from nir_block. (We could perhaps use NIR's dominance frontier information to help with this?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: a4xx encodes larger immed offsetRob Clark2015-06-214-7/+21
| | | | | | | Without this, negative branch/jump offsets look like very large positive offsets. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: simplify find_neighbors stop conditionRob Clark2015-06-211-17/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move inputs/outputs to shaderRob Clark2015-06-2112-176/+160
| | | | | | | | | These belong in the shader, rather than the block. Mostly a lot of churn and nothing too interesting. But splitting this out from the rest of ir3_block reshuffling to cut down the noise in the later patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/ra: use register_allocateRob Clark2015-06-216-481/+590
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: introduce ir3_compiler objectRob Clark2015-06-2112-31/+90
| | | | | | | | Right now, just provides a cleaner way to get at the gpu-id, given the separation between compiler and context. But we will need this also to hold the reg-set for new register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: dump nocp optionRob Clark2015-06-213-8/+0
| | | | | | No longer used, or even possible, with NIR frontend. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: silence warningsRob Clark2015-06-211-1/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove tgsi f/eRob Clark2015-06-2112-3957/+25
| | | | | | Also remove ir3_flatten which was only used by tgsi f/e. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/sched: convert to priority queueRob Clark2015-06-214-229/+242
| | | | | | | | Use a more standard priority-queue based scheduling algo. It is simpler and will make things easier once we have multiple basic blocks and flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use standard list implementationRob Clark2015-06-218-209/+161
| | | | | | | | | | Use standard list_head double-linked list and related iterators, helpers, etc, rather than weird combo of instruction array and next pointers depending on stage. Now block has an instrs_list. In certain stages where we want to remove and re-add to the blocks list we just use list_replace() to copy the list to a new list_head. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop dot graph dumpingRob Clark2015-06-2110-525/+228
| | | | | | | | At least for now.. right now the instruction and instruction list printing should suffice, and the re-working of ir3_block would require a lot of changes in that code. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: more builder helpersRob Clark2015-06-214-21/+16
| | | | | | | | Use ir3_MOV() builder in a couple of spots, rather than open-coding the instruction construction. Also add ir3_NOP() builder and use that instead of open coding. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: add missing SNERob Clark2015-06-211-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* util/list: add list_first/last_entryRob Clark2015-06-211-0/+7
| | | | | | I need an easier way to get at head/tail in ir3. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: add texture-type supportRob Clark2015-06-211-1/+43
| | | | | | | | v2: rebased on using SVIEW to hold type information Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* glsl_to_tgsi: add SVIEW decl supportRob Clark2015-06-211-1/+35
| | | | | | | | | | | | | | | | | | | | | | | Freedreno needs sampler type information to deal with int/uint textures. To accomplish this, start creating sampler-view declarations, as suggested here: http://lists.freedesktop.org/archives/mesa-dev/2014-November/071583.html create a sampler-view with index matching the sampler, to encode the texture type (ie. SINT/UINT/FLOAT). Ie: DCL SVIEW[n], 2D, UINT DCL SAMP[n] TEX OUT[1], IN[1], SAMP[n] For tgsi texture instructions which do not take an explicit SVIEW argument, the SVIEW index is implied by the SAMP index. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* util/blitter (and friends): generate appropriate SVIEW declsRob Clark2015-06-216-47/+146
| | | | | | | | Some hardware needs to know the sampler type. Update the blit related shaders to include SVIEW decl. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* util/pstipple: updates for SVIEW declsRob Clark2015-06-211-5/+17
| | | | | | | | | | To allow for shaders which use SVIEW decls for TEX* instructions, we need to preserve the constraint that the shader either has no SVIEW's or it has one matching SVIEW for each SAMP. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* draw: updates to support SVIEW declsRob Clark2015-06-212-2/+32
| | | | | | | | | | To allow for shaders which use SVIEW decls for TEX* instructions, we need to preserve the constraint that the shader either has no SVIEW's or it has one matching SVIEW for each SAMP. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* tgsi/transform: add support for SVIEW declsRob Clark2015-06-211-0/+21
| | | | | | | | | | TODO single return_type (use enum) v2: single return_type arg, and use enum Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: update docs for SVIEW usage with TEX* instructionsRob Clark2015-06-211-0/+12
| | | | | | | | | | Based on mailing list discussion here: http://lists.freedesktop.org/archives/mesa-dev/2014-November/071583.html Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Back out an accidental change I had in a VC4 commit.Eric Anholt2015-06-201-1/+0
| | | | | | This was a hack as part of debugging some glamor-on-GLES2 behavior that ended up being an xserver bug. I suspect we can just flip this extension on for GLES2, but the spec says it requires 3.1.
* vc4: Use a defined t value for 1D textures.Eric Anholt2015-06-201-1/+3
| | | | | This doesn't fix the broken 1D cases of texsubimage, but it does prevent segfaulting when dumping the QIR code generated in fbo-1d.
* vc4: Fix write-only texsubimage when we had to align.Eric Anholt2015-06-202-1/+6
| | | | | | | | We need to make sure that when we store the aligned box, we've got initialized contents in the border. We could potentially just load the border area, but for now let's get text rendering working in X (and fix the GL_TEXTURE_2D errors in piglit's texsubimage test and gl-2.1-pbo/test_tex_image)
* ilo: clean up header includesChia-I Wu2015-06-205-2/+5
| | | | Core is more self-contained now.
* ilo: avoid ilo_ib_state in genX_3DPRIMITIVE()Chia-I Wu2015-06-202-10/+8
| | | | ilo_ib_state is not in core.
* ilo: move gen6_so_SURFACE_STATE() out of coreChia-I Wu2015-06-202-52/+53
| | | | It does not belong to core.
* ilo: add ilo_state_sol_bufferChia-I Wu2015-06-206-103/+317
| | | | It serves the same purpose as ilo_state_vertex_buffer does.
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