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* nir: Add a nir_foreach_phi_src helper macroJason Ekstrand2015-01-209-11/+14
* i965: Extract scalar region checking logicBen Widawsky2015-01-203-7/+15
* i965: Add QWORD sizes to type_sz macroBen Widawsky2015-01-201-0/+3
* vc4: Fix build since 8ed5305d28d9309d651dfec3fbf4349854694694Eric Anholt2015-01-201-1/+1
* freedreno/a4xx: sysmem bypassRob Clark2015-01-201-3/+58
* freedreno: update generated headersRob Clark2015-01-205-23/+36
* radeonsi: Re-enable LLVM IR dumpsTom Stellard2015-01-201-1/+3
* radeonsi/compute: Use relocs for scratch pointer rather than user sgprs v2Tom Stellard2015-01-201-0/+42
* radeon: Teach radeon_elf_read() how to parse reloc information v3Tom Stellard2015-01-205-7/+78
* radeon: Add a helper function for freeing members of radeon_shader_binaryTom Stellard2015-01-204-6/+13
* i965: Work around mysterious Gen4 GPU hangs with minimal state changes.Kenneth Graunke2015-01-191-0/+13
* i965/nir: Enable SIMD16 support in the NIR FS backend.Kenneth Graunke2015-01-191-2/+1
* i965/nir: Use offset() instead of altering reg_offset directly.Kenneth Graunke2015-01-191-59/+32
* i965/nir: Replace fs_reg(GRF, virtual_grf_alloc(...)) with vgrf(...).Kenneth Graunke2015-01-193-13/+23
* i965: Replace fs_reg(fs_visitor, type) with fs_visitor::vgrf(type).Kenneth Graunke2015-01-196-128/+122
* st/mesa: don't set vs.key.clamp_color if a shader doesn't write any colorsMarek Olšák2015-01-193-5/+10
* winsys/radeon: increase the size of buffer cacheMarek Olšák2015-01-191-1/+1
* Rename sha1.c and sha1.h to mesa-sha1.c and mesa-sha1.hCarl Worth2015-01-193-3/+3
* mesa: fix a trivial spelling mistakeMartin Peres2015-01-191-1/+1
* mesa: support GL_RGB for GL_EXT_texture_type_2_10_10_10_REVTapani Pälli2015-01-195-0/+8
* mesa: Add ARB_shader_precision infrastructureMicah Fedke2015-01-196-1/+13
* i965/fs: Fix the dummy fragment shader.Kenneth Graunke2015-01-171-7/+32
* gbm: Define _DEFAULT_SOURCE to avoid warningKristian Høgsberg2015-01-161-0/+1
* sha1: Fix gcry_md_hd_t typo.Vinson Lee2015-01-161-1/+1
* nir: s/malloc.h/stdlib.h/Vinson Lee2015-01-161-1/+1
* i965: Fix up too-wide commentKristian Høgsberg2015-01-161-4/+3
* gbm/dri: Fix const confusionKristian Høgsberg2015-01-161-4/+3
* configure: Add machinery for --enable-shader-cache (and --disable-shader-cache)Carl Worth2015-01-163-3/+8
* mesa: Add mesa SHA-1 functionsCarl Worth2015-01-164-0/+380
* glsl: Add unit tests for blob.cCarl Worth2015-01-163-0/+328
* glsl: Add blob_overwrite_bytes and blob_overwrite_uint32Tapani Pälli2015-01-162-0/+66
* glsl: Add blob.c---a simple interface for serializing dataCarl Worth2015-01-163-0/+548
* mesa: Add iterate method for string_to_uint_mapTapani Pälli2015-01-161-0/+34
* util: Make unreachable at least be an assertCarl Worth2015-01-161-1/+1
* glsl: Add convenience function get_sampler_instanceCarl Worth2015-01-162-0/+120
* i965: Fix some oddities in FB_WRITE register width and execution size.Kenneth Graunke2015-01-161-0/+2
* i965/fs: Make lower_load_payload etc. appear in INTEL_DEBUG=optimizer.Kenneth Graunke2015-01-161-7/+11
* format_utils: Use a more precise conversion when decreasing bitsNeil Roberts2015-01-161-3/+12
* i965/gen6: Fix crash with VS+TF after rendering with GSIago Toral Quiroga2015-01-161-1/+1
* nir/live_variables: Use a worklistJason Ekstrand2015-01-151-55/+75
* nir: Add a worklist helper structureJason Ekstrand2015-01-153-0/+237
* nir: fix incorrect argument passed to validate_src() in validate_tex_instr()Brian Paul2015-01-151-1/+1
* nir: silence compiler warning from visit_src() callBrian Paul2015-01-151-1/+1
* mesa: move GET_CURRENT_CONTEXT() to top of _mesa_init_renderbuffer()Brian Paul2015-01-151-1/+2
* mesa: Fix render buffer initial internal format in GLES 3Mike Mason2015-01-151-1/+18
* util/hash_set: Rework the API to know about hashingJason Ekstrand2015-01-1515-132/+145
* util: Move main/set to util/hash_setJason Ekstrand2015-01-159-9/+8
* hash_table: Rename insert_with_hash to insert_pre_hashedJason Ekstrand2015-01-155-10/+10
* i965: Don't consider null dst instructions as matching non-null dst.Matt Turner2015-01-152-2/+4
* i965/vec4: Make sure that imm writes are to registers in the same file.Matt Turner2015-01-151-2/+8
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