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* gallium/drivers: handle PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED queryBrian Paul2013-02-048-0/+17
| | | | Initially, only softpipe/llvmpipe support SQRT.
* gallivm: implement support for SQRT opcodeBrian Paul2013-02-043-0/+37
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* tgsi: add support for new SQRT opcodeBrian Paul2013-02-044-1/+18
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* gallium: add SQRT shader opcodeBrian Paul2013-02-043-2/+12
| | | | | | | | | | | | | | | | | | The glsl-to-tgsi translater will emit SQRT to implement GLSL's sqrt() and distance() functions if the PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED query says it's supported by the driver. Otherwise, sqrt(x) is implemented with x*rsq(x). The problem with this is sqrt(0) must be handled specially because rsq(0) might be Inf/NaN/undefined (and then 0*rsq(0) is Inf/Nan/undefined). In the glsl-to-tgsi code we use an extra CMP to check if x is zero and then replace the result of x*rsq(x) with zero. In the end, this makes sqrt() generate much more reasonable code for drivers that can do square roots. Note that many of piglit's generated shader tests use the GLSL distance() function.
* radeonsi: Remove spurious traces of R16G16B16 support.Michel Dänzer2013-02-041-3/+0
| | | | | | The hardware can't do it, and these were causing warnings in some piglit tests. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Enable texture arrays.Michel Dänzer2013-02-041-1/+1
| | | | | | 28/30 piglit tests pass. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Improve packing of texture address parameters.Michel Dänzer2013-02-041-30/+97
| | | | | | | In particular, the LOD bias and depth comparison values are packed before the 'normal' texture coordinates, and the array slice and LOD values are appended. NOTE: This is a candidate for the 9.1 branch.
* radeonsi: Adapt to sample intrinsics changes.Michel Dänzer2013-02-043-51/+56
| | | | | | Fix up intrinsic names, and bitcast texture address parameters to integers. NOTE: This is a candidate for the 9.1 branch.
* st/mesa: simplify the update_single_texture() functionBrian Paul2013-02-041-28/+7
| | | | | | | | In particular, rework the sRGB/linear format selection code. There's no reason to mess with the Mesa format. Just do everything in terms of the gallium pipe_format. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: merge st_ChooseTextureFormat_renderable() into st_ChooseTextureFormat()Brian Paul2013-02-042-38/+21
| | | | That was the only place it was being called from.
* st/mesa: improve the format choosing code for DrawPixelsBrian Paul2013-02-041-6/+8
| | | | | | The code before was getting a pipe format, then calling st_pipe_format_to_mesa_format() and then converting back again with st_mesa_format_to_pipe_format(). This removes one conversion step.
* gallium: handle unhandled PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENTAndreas Boll2013-02-047-0/+8
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60098 Signed-off-by: Brian Paul <[email protected]>
* st/mesa: don't choose DXT formats if we can't do DXT compressionBrian Paul2013-02-045-13/+29
| | | | | | | | | | | | | | | | | | | | If we call gl[Copy]TexImage2D() with a generic compression format (e.g. intFormat=GL_COMPRESSED_RGBA) we can't choose a DXT format if we don't have the external DXT compression library. We weren't actually enforcing this before since the pipe_screen::is_format_supported(DXT) query has no dependency on the DXT compression library. Now if we're given a generic compressed format and we can't do DXT compression we'll fall back to a non-compressed format. v2: use util_format_is_s3tc() function and add more comments about the allow_dxt parameter. Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: don't use format chooser code for glCompressedTexImageBrian Paul2013-02-041-2/+12
| | | | | | | | | | When glCompressedTexImage is called the internalFormat is a specific format for the incoming image and the the hardware format should be the same (since we never do format transcoding). So use the simpler _mesa_glenum_to_compressed_format() function. This change is also needed for the next patch. Note: This is a candidate for the stable branches.
* i965: Fix the SF Vertex URB Read Length calculation for Gen7 platforms.Kenneth Graunke2013-02-031-16/+16
| | | | | | | | | | | | | | | | | | | Ivybridge doesn't appear to have the same errata as Sandybridge; no corruption was observed by setting it to more than the minimal correct value. It's possible that we were simply lucky, since the URB entries are 1024-bit on Ivybridge vs. 512-bit Sandybridge. Or perhaps the underlying hardware issue is fixed. Either way, we may as well program the minimum value since it's now readily available, likely to be more efficient, and possibly more correct. v2: Use GEN7_SBE_* defines rather than GEN6_SF_*. (A copy and paste mistake.) They're the same, but using the right names is better. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix the SF Vertex URB Read Length calculation for Sandybridge.Kenneth Graunke2013-02-031-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This commit message was primarily written by Paul Berry, who explained what's going on far better than I would have.) Previous to this patch, we thought that the only restrictions on 3DSTATE_SF's URB read length were (a) it needs to be large enough to read all the VUE data that the SF needs, and (b) it can't be so large that it tries to read VUE data that doesn't exist. Since the VUE map already tells us how much VUE data exists, we didn't bother worrying about restriction (a); we just did the easy thing and programmed the read length to satisfy restriction (b). However, we didn't notice this erratum in the hardware docs: "[errata] Corruption/Hang possible if length programmed larger than recommended". Judging by the context surrounding this erratum, it's pretty clear that it means "URB read length must be exactly the size necessary to read all the VUE data that the SF needs, and no larger". Which means that we can't program the read length based on restriction (b)--we have to program it based on restriction (a). The URB read size needs to precisely match the amount of data that the SF consumes; it doesn't work to simply base it on the size of the VUE. Thankfully, the PRM contains the precise formula the hardware expects. Fixes random UI corruption in Steam's "Big Picture Mode", random terrain corruption in PlaneShift, and Piglit's fbo-5-varyings test. NOTE: This is a candidate for all stable branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56920 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60172 Tested-by: Jordan Justen <[email protected]> (v1/Piglit) Tested-by: Martin Steigerwald <[email protected]> (PlaneShift) Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Compute the maximum SF source attribute.Kenneth Graunke2013-02-033-4/+12
| | | | | | | | | | The maximum SF source attribute is necessary to compute the Vertex URB read length properly, which will be done in the next commit. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Tested-by: Martin Steigerwald <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Refactor Gen6+ SF attribute override code.Kenneth Graunke2013-02-031-12/+13
| | | | | | | | | | | The next patch will benefit from easy access to the source attribute number and whether or not we're swizzling. It doesn't want the final attr_override DWord form, however. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Tested-by: Martin Steigerwald <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: Remove hash table from ir_set_program_inouts pass.Kenneth Graunke2013-02-031-24/+14
| | | | | | | | | | | Back when ir_var_in and ir_var_out signified both function parameters and shader input/outputs, we had trouble distinguishing the two when looking at a dereference. Now that we have separate ir_var_shader_in and ir_var_shader_out modes, we can determine this easily. Removing the hash table saves memory and CPU overhead. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove dead field brw_wm_prog_data::error.Kenneth Graunke2013-02-031-1/+0
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* i965: Remove dead field brw_context::constant_map.Kenneth Graunke2013-02-031-1/+0
| | | | This was used by the old VS backend, but that's long gone.
* r600g: Fix memory leak.Vinson Lee2013-02-011-1/+3
| | | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* egl/dri2: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv30: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv50: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* swrast: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g/llvm: Select the correct GPU type for RV670Tom Stellard2013-02-011-1/+1
| | | | | | | | RV670 belongs in the R600 chip class https://bugs.freedesktop.org/show_bug.cgi?id=58666 NOTE: This is a candidate for the 9.1 branch
* intel: implement create image from textureAbdiel Janulgue2013-02-011-21/+138
| | | | | | | | | | | | | | | | | Save miptree level info to DRIImage: - Appropriately-aligned base offset pointing to the image - Additional x/y adjustment offsets from above. v8: -Bump intelImageExtension version v9: -Don't use internal _eglError but implement error reporting in new DRI inteface instead. This fixes Android build problems based on feedback from Adrian M Negreanu and Chad Versace. -Move the non-tile-aligned check and error-reporting to intel_set_texture_image_region v10: -Don't #include "egl/main/eglcurrent.h". [chadv] Reviewed-by: Eric Anholt <[email protected]> (v6) Acked-by: Chad Versace <[email protected]> (v10) Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: Account for mt->offset in intel_miptree_mapAbdiel Janulgue2013-02-011-2/+2
| | | | | | | | | | | We need to take account the offset from original bo when using glTexSubImage() and other functions that manipulate the subregion of an exported texture. Offsets are appended to mapped region address and when blitting from a source region. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: Create a miptree using offsets in intel_set_texture_image_regionAbdiel Janulgue2013-02-011-7/+53
| | | | | | | | | | | | | | | | When binding a region to a texture image, re-create the miptree base-level considering the offset and dimension information exported by DRIImage. v8: - Move the alignment surface address checks from the image-from-texture code to the texture-from-image side. This allows the error reporting to conform to OES_EGL_Image and to prevent mixing up EGL and GL errors. Reported by Chad Versace. - Addressed an existing issue in renderbuffer case where there is a a possibility of creating EGL images out of depthstencil textures which isn't really possible. This was spotted by Eric earlier. Reviewed-by: Eric Anholt <[email protected]> (v6) Reviewed-by: Chad Versace <[email protected]> (v8) Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Account for offsets when updating SURFACE_STATE.Abdiel Janulgue2013-02-012-2/+21
| | | | | | | | | If the offsets are present, this lets us specify a particular level and slice in a shared region using the base level of an exported mip-map tree. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: add pixel offset calculator for miptree levelsAbdiel Janulgue2013-02-012-0/+21
| | | | | | | | | Add helper to calculate fine-grained x and y adjustment pixels to an image within a miptree level for tiled regions. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: Expose intel_miptree_create_internal as intel_miptree_create_layout.Abdiel Janulgue2013-02-012-14/+25
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: expose dimensions and offsets of a miptree level in DRIImageAbdiel Janulgue2013-02-011-0/+7
| | | | | | | | v8: - Append has_depthstencil field in DRIImage structure. Reviewed-by: Eric Anholt <[email protected]> (v6) Reviewed-by: Chad Versace <[email protected]> (v8) Signed-off-by: Abdiel Janulgue <[email protected]>
* dri2: Create image from textureAbdiel Janulgue2013-02-011-0/+122
| | | | | | | | | | | Add create image from texture extension and bump version. v8: - Add appropriate image errors codes in DRI interface so we don't have to use internal EGL functions in driver. Suggested by Chad Versace. Reviewed-by: Eric Anholt <[email protected]> (v6) Reviewed-by: Chad Versace <[email protected]> (v8) Signed-off-by: Abdiel Janulgue <[email protected]>
* radeonsi: Fix draws using user index buffer.Michel Dänzer2013-02-011-4/+3
| | | | | | | | | Was broken since commit bf469f4edc60bd1c5fd770cb231b8d5ab801427f ('gallium: add void *user_buffer in pipe_index_buffer'). Fixes 11 piglit tests and lots of missing geometry e.g. in TORCS. NOTE: This is a candidate for the 9.1 branch.
* st/mesa: whitespace/indentation fixBrian Paul2013-02-011-2/+2
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* svga: check for NaN shader immediatesBrian Paul2013-02-011-2/+4
| | | | | | | The svga device doesn't handle them. Replace with zeros. Fixes several piglit tests, such as "glsl-const-builtin-inversesqrt". Reviewed-by: Reviewed-by: José Fonseca <[email protected]>
* svga: add, use SVGA3D_SURFACE_HINT_VOLUME flagBrian Paul2013-02-012-0/+5
| | | | Reviewed-by: Reviewed-by: José Fonseca <[email protected]>
* trace: measure time for each gallium callBrian Paul2013-02-013-3/+39
| | | | | To get a rough idea of how much time is spent in each gallium driver function. The time is measured in microseconds.
* trace: add void to function definitionBrian Paul2013-02-011-1/+2
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* trace: allow GALLIUM_TRACE=stdout/stderrBrian Paul2013-02-011-3/+11
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* radeonsi: port some of get_shader_param changes from r600gMarek Olšák2013-02-011-6/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* mesa: don't expose IBM_rasterpos_clip in a core contextMarek Olšák2013-02-011-1/+1
| | | | | | | | | glRasterPos doesn't exist in the core profile. NOTE: This is a candidate for the stable branches (9.0 and 9.1). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r300g: always put MSAA resources in VRAMMarek Olšák2013-02-011-3/+3
| | | | | | | | | This along with the latest drm-fixes branch should help with bad performance of MSAA. Remember: Nx MSAA can't be more than N times slower (where N=2,4,6). Anyway, I recommend at least 512 MB of VRAM for Full HD 6x MSAA. NOTE: This is a candidate for the 9.1 branch.
* r600g: remove broken assert from r600_isa.cVadim Girlin2013-02-011-2/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: implement shader disassembler v3Vadim Girlin2013-02-013-4/+444
| | | | | | | | | | | | | | R600_DUMP_SHADERS environment var now allows to choose dump method: 0 (default) - no dump 1 - full dump (old dump) 2 - disassemble 3 - both v2: fix output for burst_count > 1 v3: use more human-readable output for kcache data in CF_ALU_xxx clauses, improve output for ALU_EXTENDED, other minor fixes Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use tables with ISA info v3Vadim Girlin2013-02-0110-1789/+2378
| | | | | | | | | v3: added some flags including condition codes for ALU, fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx and other CF instructions) rebased on current master Signed-off-by: Vadim Girlin <[email protected]>
* glapi: Do not use backtrace on MinGW.Vinson Lee2013-01-311-1/+1
| | | | | | | execinfo.h is not available on MinGW. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
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