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* panfrost: Align Android makefiles with recent changesRoman Stratiienko2020-03-234-1/+62
| | | | | | | Reviewed-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Roman Stratiienko <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4280>
* pan/bi: Pack csel4 opcodesAlyssa Rosenzweig2020-03-222-1/+80
| | | | | | | | | | | | | | These are pretty straightforward but there's a lot of details to keep straight. In the IR, we keep a general logical comparator and types separately; in the hardware, the type gets fused with a (much more) limited number of comparators. So there's a fair bit of code here to account for these differences, fusing in the type information, and changing up argument order as necessary to make it actually correct. Anything to save a bit! Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Default csel to "!= 0" modeAlyssa Rosenzweig2020-03-221-0/+5
| | | | | | | | This way we always have regular csel conditions instead of a weird .always special case for 3-src CSEL mode. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Use bi_lookup_immediate when packingAlyssa Rosenzweig2020-03-221-15/+25
| | | | | | | | This gets us part of the way there to packing lo/hi separately. A little more work is needed to do this "properly", but hey. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Respect shift when printing immediatesAlyssa Rosenzweig2020-03-223-2/+11
| | | | | | | | We allow packing multiple immediates in, but we were missing this in the print. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Implement csel fusingAlyssa Rosenzweig2020-03-221-21/+65
| | | | | | | | | When generating csel instructions, we can peak to see what condition is being used. If we're using a "nice" condition, we can fuse it in with the csel itself, ideally letting the condition itself be DCE'd away. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Add `soft` NIR->BIR condition translationAlyssa Rosenzweig2020-03-221-3/+11
| | | | | | | | | We would like to use this routine opportunistically when fusing conditions into csels and branches, so let's add a mode where we don't abort. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Remove hacks for 1-bit booleans in IRAlyssa Rosenzweig2020-03-224-8/+8
| | | | | | | Now that we lower them away, a bunch of special cases disappear. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Lower bool to intsAlyssa Rosenzweig2020-03-222-27/+39
| | | | | | | | Currently we lower to int32, but once mediump lands we'll be ready for that too. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack LD_ATTRAlyssa Rosenzweig2020-03-223-11/+39
| | | | | | | Also requires the usual R61/62 games. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack st_varyAlyssa Rosenzweig2020-03-222-0/+29
| | | | | | | This should let varying writes go through finally. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Add store_channels propertyAlyssa Rosenzweig2020-03-223-1/+7
| | | | | | | | It can't be inferred from the usual writemask since stores don't write to a register destination. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Generalize data register settingAlyssa Rosenzweig2020-03-221-3/+15
| | | | | | | So we can use it for stores too. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Flesh out st_vary IRAlyssa Rosenzweig2020-03-224-15/+16
| | | | | | | | | We need to make the semantics of BI_VECTOR a bit more precise - vectorize only the first argument, not all of them. This is enough for current and future users, as far as I know. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack ld_var_addrAlyssa Rosenzweig2020-03-224-1/+42
| | | | | | | Choo choo. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack ld_ubo opsAlyssa Rosenzweig2020-03-222-0/+50
| | | | | | | | Routes some infrastructure to do so at least slightly generically but we'll see. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Add bi_load32_components helperAlyssa Rosenzweig2020-03-222-0/+11
| | | | | | | Pattern seems to crop up a lot. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Include UBO index for sysval readsAlyssa Rosenzweig2020-03-221-1/+1
| | | | | | | Trivially zero. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Index out constants in instructionsAlyssa Rosenzweig2020-03-221-28/+90
| | | | | | | | | | | We rewrite BIR_INDEX_CONSTANT (and _ZERO) to preassigned constant ports when assign uniform_const for the bundle. There are a lot of issues raised here, unfortunately, and the implementation here is woefully incomplete with a nasty hack for loads... nevertheless, it's somewhere to start. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Document constant related errata(?)Alyssa Rosenzweig2020-03-221-0/+5
| | | | | | | | | | We're not totally sure what's up with this but Connor says if you violate it Bad Things happen in your shader. I think this might be an issue affecting early Bifrost (G71, ..?); when we know more we can look into patching in a fix. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack a constant quadwordAlyssa Rosenzweig2020-03-222-1/+50
| | | | | | | | The piping isn't there to make use of it yet, but this stubs out constant support at the clause level. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Add move lowering passAlyssa Rosenzweig2020-03-221-0/+43
| | | | | | | | | We need ALU mostly scalarized, but we get vector moves created from lower_vec_to_mov so let's scalarize that ourselves rather than bother NIR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Add bi_emit_before helperAlyssa Rosenzweig2020-03-221-0/+9
| | | | | | | For BIR lowering passes. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Implement FMA/MOV without modifiersAlyssa Rosenzweig2020-03-225-5/+26
| | | | | | | | | | We split off MOV from FMOV since the canonical move on Bifrost doesn't accept modifiers. (We can still do fmov, but with something like add-0.) This will also make copyprop a little nicer, I think. Anyway, the non-modifier version we can implement as-is for FMA. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4276>
* pan/bi: Pack BI_BLENDAlyssa Rosenzweig2020-03-192-0/+18
| | | | | | | | MRT not yet supported to keep things easy. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Flesh out BI_BLENDAlyssa Rosenzweig2020-03-191-1/+7
| | | | | | | It ingests the output of ATEST, whatever that actually is. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add ATEST packingAlyssa Rosenzweig2020-03-192-0/+38
| | | | | | | Only fp32 for now. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Flesh out ATEST in IRAlyssa Rosenzweig2020-03-192-2/+17
| | | | | | | | ATEST actually takes two sources and has a destination. Although the details are a little funny, we should still model this correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Track clause types during schedulingAlyssa Rosenzweig2020-03-191-0/+47
| | | | | | | | | | | There's an easy mapping for this, so let's do it. Note we do this at schedule-time instead of emit since we'll need to lookahead clause types. The alternative is a prepass running after schedule but before codegen, but there's no reason not to just stick it here when we're preparing bi_clause in the first place. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Don't hide SCHED_ADD inside HI_LATENCYAlyssa Rosenzweig2020-03-192-13/+13
| | | | | | | It makes bitwise property checking annoying. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pretty-print clause types in disassemblerAlyssa Rosenzweig2020-03-194-3/+40
| | | | | | | Also note that type=1 is for load_vary. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Route through clause headerAlyssa Rosenzweig2020-03-192-5/+26
| | | | | | | | We already track almost all the information we need, let's dump it onto the wire now. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Skip over data registers in port assignmentAlyssa Rosenzweig2020-03-193-10/+28
| | | | | | | | They bypass the usual mechanism entirely, let's add some props to describe this and respect them. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Emit load_vary opsAlyssa Rosenzweig2020-03-192-0/+45
| | | | | | | | Annoyingly long code to do so, but this should theoretically work for both direct and indirect load_vary. Still need to handle destination. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pass second src for load_vary opsAlyssa Rosenzweig2020-03-191-1/+10
| | | | | | | | | For direct, this is just 0, but for indirct, this is a sample mask preloaded in R61. Handle this at code emit time instead of trying to do crazy monkeypatching later. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Generalize bi_get_src a bitAlyssa Rosenzweig2020-03-191-8/+33
| | | | | | | | Allow it to work with ADD ops and stub out some immediate fetching infrastructure (currently only works with 0). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: List ADD classes in bi_pack_addAlyssa Rosenzweig2020-03-191-2/+32
| | | | | | | Handling will be... somewhat tricky. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack fadd32Alyssa Rosenzweig2020-03-192-0/+25
| | | | | | | Choo choo. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack BI_FMA opsAlyssa Rosenzweig2020-03-191-6/+84
| | | | | | | | | | This is our first instruction we've emitted, requiring us to pipe through registes/ports and various details from the IR. It's quite a bit of code, but overall I'm happy with this structure. With some tedium we should be able to emit the rest of the ALU ops this way, too. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add struct bifrost_fma_fmaAlyssa Rosenzweig2020-03-191-0/+16
| | | | | | | So we can pack regular FMA ops. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Model 3-bit Bifrost srcs in IRAlyssa Rosenzweig2020-03-192-1/+14
| | | | | | | | We'll want to set these manually for schedule-time passthrough, as well as use the enum for packing. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Route through first_instruction fieldAlyssa Rosenzweig2020-03-191-2/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Assign registers to portsAlyssa Rosenzweig2020-03-191-9/+86
| | | | | | | | | | Now that we can pack registers given the assigned ports, and we can assign registers from the indices, the missing link is assigning ports from the registers, and now finally we get some real data showing up in a disassembly exercising lots of different code paths. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add missing __attribute__((packed))Alyssa Rosenzweig2020-03-191-13/+13
| | | | | | | That this code worked before makes me rather nervous... Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack register fieldsAlyssa Rosenzweig2020-03-191-4/+53
| | | | | | | Now that we have ctrl, the rest is natural... sorta. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add packing for register control fieldAlyssa Rosenzweig2020-03-192-2/+86
| | | | | | | | Filling in some gaps based on intuition from the bit patterns but this should be vaguely right. More investigation needed down the line. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Sketch out instruction word packingAlyssa Rosenzweig2020-03-192-2/+51
| | | | | | | | Instructions are 78-bits with some seriously suspicious packing requirements but hey, gotta save 'em bits. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Setup initial clause packingAlyssa Rosenzweig2020-03-195-0/+116
| | | | | | | | | At the moment, we just iterate the clauses in the post-RA, post-sched IR and generate a dummy clause corresponding, passing the results to the disassembler to verify. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Interpret register allocation resultsAlyssa Rosenzweig2020-03-122-0/+96
| | | | | | | | | | | | Once LCRA has run, we have a map from IR indices to byte offsets into the register file, so we need to "install" these results, rewriting the IR to use native registers and fixing up writemasks/swizzles to substitute vectorization for adjacent registers (for LCRA, we're modeling in terms of real vectors). Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Add register allocatorAlyssa Rosenzweig2020-03-124-1/+116
| | | | | | | | | | We model the machine as vector (with restrictions) to natively handle mixed types and I/O and other goodies. We use LCRA for the heavylifting. This commit adds only the modeling to feed into LCRA and spit LCRA solutions back; next commit will integrate it with the IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 12:32:10 +0000