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* panfrost: Rework midgard_pair_load_store() to kill the nested foreach loopBoris Brezillon2019-09-131-34/+29
| | | | | | | | | | | | | | | | | | | | | | | mir_foreach_instr_in_block_safe() is based on list_for_each_entry_safe() which is designed to protect against removal of the current entry, but removing the entry placed just after the current one will lead to a use-after-free situation. Luckily, the midgard_pair_load_store() logic guarantees that the instruction being removed (if any) is never placed just after ins which in turn guarantees that the hidden __next variable always points to a valid object. Took me a bit of time to realize that this code was safe, so I'm suggesting to get rid of the inner mir_foreach_instr_in_block_from() loop and rework the code so that the removed instruction is always the current one (which is what the list_for_each_entry_safe() API was initially designed for). While at it, we also get rid of the unecessary insert(ins)/remove(ins) dance by simply moving the instruction around. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Fix a list_assert() in schedule_block()Boris Brezillon2019-09-131-4/+6
| | | | | | | | | list_for_each_entry() does not allow modifying the current item pointer. Let's rework the skip-instructions logic in schedule_block() to not break this rule. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* nir: allow specifying filter callback in lower_alu_to_scalarVasily Khoruzhick2019-09-062-2/+2
| | | | | | | | | | | | | Set of opcodes doesn't have enough flexibility in certain cases. E.g. Utgard PP has vector conditional select operation, but condition is always scalar. Lowering all the vector selects to scalar increases instruction number, so we need a way to filter only those ops that can't be handled in hardware. Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* pan/midgard: Remove mir_rewrite_index_*_tagAlyssa Rosenzweig2019-09-032-29/+0
| | | | | | | These helpers are unused, as flagged by cppcheck. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Remove mir_print_bundleAlyssa Rosenzweig2019-09-031-13/+0
| | | | | | | In practice, the new post-schedule print is just as useful. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Remove cppwrap.cppAlyssa Rosenzweig2019-09-032-10/+0
| | | | | | | | It has not been used in a long time; I forgot this file even existed. Flagged by cppcheck. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Fix cppcheck issuesAlyssa Rosenzweig2019-09-035-22/+27
| | | | | | | Miscellaneous minor issues flagged by cppcheck. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Correct issues in disassemble.cAlyssa Rosenzweig2019-09-031-23/+22
| | | | | | | cppcheck. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/decode: Add missing format specifierAlyssa Rosenzweig2019-09-031-1/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/decode: Use portable format specifier for 64-bitAlyssa Rosenzweig2019-09-031-1/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/decode: Use %zu instead of %dAlyssa Rosenzweig2019-09-031-3/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/decode: Fix uninitialized variablesAlyssa Rosenzweig2019-09-031-2/+5
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Use shared psiz clamp passAlyssa Rosenzweig2019-08-302-6/+1
| | | | | | | We already had a perfectly cromulent pass for this, but one landed in common NIR code so let's switch and lighten our tree. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Remove mir_opt_post_move_eliminateAlyssa Rosenzweig2019-08-302-49/+0
| | | | | | | This optimization depended on RA running before scheduling. It therefore no longer applies and is now unused. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Schedule before RAAlyssa Rosenzweig2019-08-301-27/+29
| | | | | | | | | | | | | | | | | | | | | This is a tradeoff. Scheduling before RA means we don't do RA on what-will-become pipeline registers. Importantly, it means the scheduler is able to reorder instructions, as registers have not been decided yet. Unfortunately, it also complicates register spilling, since the spills themselves won't get bundled optimally and we can only spill twice per ALU bundle (only one spill per bundle allowed here). It also prevents us from eliminating dead moves introduced by register allocation, as they are not dead before RA. The shader-db regressions are from poor spilling choices introduced by the new bundling requirements. These could be solved by the combination of a post-scheduler (to combine adjacent spills into bundles) with a VLIW-aware spill cost calculation. Nevertheless, the change is small enough that I feel it's worth it to eat a tiny shader-db regression for the sake of flexibility. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Handle fragment writeout in RAAlyssa Rosenzweig2019-08-306-24/+49
| | | | | | | | | | Rather than using a pile of hacks and awkward constructs in MIR to ensure the writeout parameter gets written into r0, let's add a dedicated shadow register class for writeout (interfering with work register r0) so we can express the writeout condition succintly and directly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Do not propagate swizzles into writeoutAlyssa Rosenzweig2019-08-301-3/+5
| | | | | | | There's no slot for it; you'll end up writing into the void and clobbering stuff. Don't. do it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix misc. RA issuesAlyssa Rosenzweig2019-08-301-10/+15
| | | | | | | | When running the register allocator after scheduling, the MIR looks a little different, so we need to extend the RA to handle a few of these extra cases correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Print MIR by the bundleAlyssa Rosenzweig2019-08-301-2/+11
| | | | | | | After scheduling, we still have valid MIR, but we have additional bundling annotations which we would like to keep debug, so print these. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Print branches in MIRAlyssa Rosenzweig2019-08-301-1/+8
| | | | | | | Rather than a vague "br.??" line, annotate the branch with its target type (useful for disambiguating discards) and whether it was inverted. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Remove texture_indexAlyssa Rosenzweig2019-08-302-6/+0
| | | | | | This is deadcode. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Cleanup fragment writeout branchAlyssa Rosenzweig2019-08-301-2/+3
| | | | | | | I'm not sure if this is strictly necessary but it makes debugging easier and minimizes the diff with the experimental scheduler. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add scheduling barriersAlyssa Rosenzweig2019-08-301-38/+42
| | | | | | | | | | | | | | | | Scheduling occurs on a per-block basis, strongly assuming that a given block contains at most a single branch. This does not always map to the source NIR control flow, particularly when discard intrinsics are involved. The solution is to allow scheduling barriers, which will terminate a block early in code generation and open a new block. To facilitate this, we need to move some post-block processing to a new pass, rather than relying hackily on the current_block pointer. This allows us to cleanup some logic analyzing branches in other parts of the driver us well, now that the MIR is much more well-formed. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Track shader quadword count while schedulingAlyssa Rosenzweig2019-08-303-7/+7
| | | | | | | This allow multiblock blend shaders to compute constant colour offsets correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Allow NULL argument in mir_has_argAlyssa Rosenzweig2019-08-301-0/+3
| | | | | | | | It's sometimes convenient to call this with no instruction specified. By definition, a missing instruction cannot reference any argument, so let's check for NULL and shortciruit to false. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Improve mir_mask_of_read_componentsAlyssa Rosenzweig2019-08-301-2/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend mir_special_index to writeoutAlyssa Rosenzweig2019-08-301-1/+2
| | | | | | | The branch has the writeout specified in its source list, making this special even if it's not explicitly part of r0. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: csel_swizzle with mir get swizzleAlyssa Rosenzweig2019-08-301-0/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_insert_instruction*scheduled helpersAlyssa Rosenzweig2019-08-302-0/+91
| | | | | | | | | | | | | | | In order to run register allocation after scheduling, it is sometimes necessary to be able to insert instructions into an already-scheduled program. This is suboptimal, since it forces us to do a worst-case scheduling, but it is nevertheless required for correct handling of spills/fills. Let's add helpers to insert instructions as standalone bundles for use in spilling code. These helpers are minimal -- they *only* work on load/store ops or moves. They should not be used for anything but register spilling; any other instructions should be added prior to the schedule. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Track csel swizzleAlyssa Rosenzweig2019-08-302-4/+17
| | | | | | | | | While it doesn't matter with an unconditional move to the conditional register (r31), when we try to elide that move we'll need to track the swizzle explicitly, and there is no slot for that yet since ALU ops are normally binary. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Ensure fragment writeout is in the final blockAlyssa Rosenzweig2019-08-302-9/+6
| | | | | | | This ensures the block only has exactly one branch, which makes scheduling happy. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Document Midgard scheduling requirementsAlyssa Rosenzweig2019-08-301-0/+29
| | | | | | | Oh boy. Midgard scheduling is crazy... These are all just the requirements, not even the algorithm yet. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Include condition in branch->src[0]Alyssa Rosenzweig2019-08-301-0/+5
| | | | | | This will allow us to reference the condition while scheduling. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add post-schedule iteration helpersAlyssa Rosenzweig2019-08-301-0/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix corner case in RAAlyssa Rosenzweig2019-08-301-1/+1
| | | | | | It doesn't really matter but... meh. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add OP_IS_CSEL_V helperAlyssa Rosenzweig2019-08-301-2/+6
| | | | | | ..to distinguish from scalar csel. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Expose mir_get/set_swizzleAlyssa Rosenzweig2019-08-302-2/+4
| | | | | | The scheduler would like to use these. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extract instruction sizing helperAlyssa Rosenzweig2019-08-301-15/+19
| | | | | | The scheduler shouldn't need to worry about this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Factor out mir_is_scalarAlyssa Rosenzweig2019-08-301-33/+42
| | | | | | This helper doesn't need to be in the giant loop. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Count shader-db stats by bundled instructionsAlyssa Rosenzweig2019-08-301-4/+3
| | | | | | | | | | | This does not affect shaders in any way. Rather, it makes the shader-db instruction count recorded in the compiler accurate with the in-order scheduler, matching up with what we calculate from pandecode. Though shaders are the same, instruction counts cannot be compared across this commit for this reason. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use ralloc() to allocate instructions to avoid leaking those objsBoris Brezillon2019-08-288-16/+17
| | | | | | | | | Instructions attached to blocks are never explicitly freed. Let's use ralloc() to attach those objects to the compiler context so that they are automatically freed when the ctx object is freed. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* Revert "panfrost: Free all block/instruction objects before leaving ↵Boris Brezillon2019-08-272-15/+0
| | | | | | | | | | midgard_compile_shader_nir()" This reverts commit 5882e0def97a47aff050f5a3f412b97a7f440e27. This commit causes a segfault. Signed-off-by: Boris Brezillon <[email protected]>
* panfrost: Make sure bundle.instructions[] contains valid instructionsBoris Brezillon2019-08-271-0/+1
| | | | | | | | Add an assert() in schedule_bundle() to make sure all instruction pointers in bundle.instructions[] are valid. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Free all block/instruction objects before leaving ↵Boris Brezillon2019-08-272-0/+15
| | | | | | | | | | | midgard_compile_shader_nir() Right now we're leaking all block and instruction objects allocated by the compiler. Let's clean things up before leaving midgard_compile_shader_nir(). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Free the instruction object in mir_remove_instruction()Boris Brezillon2019-08-271-0/+1
| | | | | | | To avoid memory leaks. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix invert fusing with r26Alyssa Rosenzweig2019-08-262-2/+19
| | | | | | The invert wasn't applying (correctly) due to the issues addressed here. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fold ssa_args into midgard_instructionAlyssa Rosenzweig2019-08-2616-249/+210
| | | | | | This is just a bit of refactoring to simplify MIR. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add imov->fmov optimizationAlyssa Rosenzweig2019-08-264-0/+85
| | | | | | | | | | | | | | | | | | When moving constants, if switching to a floating-point representation doesn't break anything, we'd rather have an fmov than an imov, permitting inlining the constant in many circumstances. total quadwords in shared programs: 3408 -> 3366 (-1.23%) quadwords in affected programs: 1188 -> 1146 (-3.54%) helped: 41 HURT: 0 helped stats (abs) min: 1 max: 2 x̄: 1.02 x̃: 1 helped stats (rel) min: 0.19% max: 25.00% x̄: 9.65% x̃: 11.11% 95% mean confidence interval for quadwords value: -1.07 -0.98 95% mean confidence interval for quadwords %-change: -11.38% -7.93% Quadwords are helped. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Switch constants to uint32Alyssa Rosenzweig2019-08-263-10/+17
| | | | | | | | Storing constants as float doesn't make sense when we have integer instructions; better to switch to be integer natively and coerce to/from float rather than the opposite. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard, bifrost: Set lower_fdph = trueAlyssa Rosenzweig2019-08-262-0/+2
| | | | | | fdph instructions show up in some desktop GL shaders. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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