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* pan/bi: Pack BI_BLENDAlyssa Rosenzweig2020-03-192-0/+18
| | | | | | | | MRT not yet supported to keep things easy. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Flesh out BI_BLENDAlyssa Rosenzweig2020-03-191-1/+7
| | | | | | | It ingests the output of ATEST, whatever that actually is. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add ATEST packingAlyssa Rosenzweig2020-03-192-0/+38
| | | | | | | Only fp32 for now. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Flesh out ATEST in IRAlyssa Rosenzweig2020-03-192-2/+17
| | | | | | | | ATEST actually takes two sources and has a destination. Although the details are a little funny, we should still model this correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Track clause types during schedulingAlyssa Rosenzweig2020-03-191-0/+47
| | | | | | | | | | | There's an easy mapping for this, so let's do it. Note we do this at schedule-time instead of emit since we'll need to lookahead clause types. The alternative is a prepass running after schedule but before codegen, but there's no reason not to just stick it here when we're preparing bi_clause in the first place. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Don't hide SCHED_ADD inside HI_LATENCYAlyssa Rosenzweig2020-03-192-13/+13
| | | | | | | It makes bitwise property checking annoying. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pretty-print clause types in disassemblerAlyssa Rosenzweig2020-03-194-3/+40
| | | | | | | Also note that type=1 is for load_vary. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Route through clause headerAlyssa Rosenzweig2020-03-192-5/+26
| | | | | | | | We already track almost all the information we need, let's dump it onto the wire now. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Skip over data registers in port assignmentAlyssa Rosenzweig2020-03-193-10/+28
| | | | | | | | They bypass the usual mechanism entirely, let's add some props to describe this and respect them. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Emit load_vary opsAlyssa Rosenzweig2020-03-192-0/+45
| | | | | | | | Annoyingly long code to do so, but this should theoretically work for both direct and indirect load_vary. Still need to handle destination. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pass second src for load_vary opsAlyssa Rosenzweig2020-03-191-1/+10
| | | | | | | | | For direct, this is just 0, but for indirct, this is a sample mask preloaded in R61. Handle this at code emit time instead of trying to do crazy monkeypatching later. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Generalize bi_get_src a bitAlyssa Rosenzweig2020-03-191-8/+33
| | | | | | | | Allow it to work with ADD ops and stub out some immediate fetching infrastructure (currently only works with 0). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: List ADD classes in bi_pack_addAlyssa Rosenzweig2020-03-191-2/+32
| | | | | | | Handling will be... somewhat tricky. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack fadd32Alyssa Rosenzweig2020-03-192-0/+25
| | | | | | | Choo choo. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack BI_FMA opsAlyssa Rosenzweig2020-03-191-6/+84
| | | | | | | | | | This is our first instruction we've emitted, requiring us to pipe through registes/ports and various details from the IR. It's quite a bit of code, but overall I'm happy with this structure. With some tedium we should be able to emit the rest of the ALU ops this way, too. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add struct bifrost_fma_fmaAlyssa Rosenzweig2020-03-191-0/+16
| | | | | | | So we can pack regular FMA ops. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Model 3-bit Bifrost srcs in IRAlyssa Rosenzweig2020-03-192-1/+14
| | | | | | | | We'll want to set these manually for schedule-time passthrough, as well as use the enum for packing. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Route through first_instruction fieldAlyssa Rosenzweig2020-03-191-2/+3
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Assign registers to portsAlyssa Rosenzweig2020-03-191-9/+86
| | | | | | | | | | Now that we can pack registers given the assigned ports, and we can assign registers from the indices, the missing link is assigning ports from the registers, and now finally we get some real data showing up in a disassembly exercising lots of different code paths. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add missing __attribute__((packed))Alyssa Rosenzweig2020-03-191-13/+13
| | | | | | | That this code worked before makes me rather nervous... Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Pack register fieldsAlyssa Rosenzweig2020-03-191-4/+53
| | | | | | | Now that we have ctrl, the rest is natural... sorta. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Add packing for register control fieldAlyssa Rosenzweig2020-03-192-2/+86
| | | | | | | | Filling in some gaps based on intuition from the bit patterns but this should be vaguely right. More investigation needed down the line. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Sketch out instruction word packingAlyssa Rosenzweig2020-03-192-2/+51
| | | | | | | | Instructions are 78-bits with some seriously suspicious packing requirements but hey, gotta save 'em bits. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Setup initial clause packingAlyssa Rosenzweig2020-03-195-0/+116
| | | | | | | | | At the moment, we just iterate the clauses in the post-RA, post-sched IR and generate a dummy clause corresponding, passing the results to the disassembler to verify. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
* pan/bi: Interpret register allocation resultsAlyssa Rosenzweig2020-03-122-0/+96
| | | | | | | | | | | | Once LCRA has run, we have a map from IR indices to byte offsets into the register file, so we need to "install" these results, rewriting the IR to use native registers and fixing up writemasks/swizzles to substitute vectorization for adjacent registers (for LCRA, we're modeling in terms of real vectors). Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Add register allocatorAlyssa Rosenzweig2020-03-124-1/+116
| | | | | | | | | | We model the machine as vector (with restrictions) to natively handle mixed types and I/O and other goodies. We use LCRA for the heavylifting. This commit adds only the modeling to feed into LCRA and spit LCRA solutions back; next commit will integrate it with the IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Fix missing src_typesAlyssa Rosenzweig2020-03-121-0/+7
| | | | | | | | We want types to be consistent throughout the IR so we don't have to make exceptions to parse things out. These cases just got missed. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Fix vector handling of readmasksAlyssa Rosenzweig2020-03-123-10/+46
| | | | | | | | | | | | The issue was messing with liveness analysis... with Midgard we look at the writemask to decide how the instruction behaves. Here, since our ALU is scalar (except for subdivision which doesn't have proper writemasks anyway) we just look at the component count directly -- either 4 for vector instructions (essentially - for smaller loads we can replicate manually without much burden), or 1 for scalar. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Minor fixes in iteration macrosAlyssa Rosenzweig2020-03-121-9/+9
| | | | | | | Found during RA bringup. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/midgard: Remove incorrect comment in RAAlyssa Rosenzweig2020-03-121-7/+0
| | | | | | | | Ironically, this comment was mistakenly added by the commit that fixed the purported issue in the comment (1bce7fdecd86 - found by `git blame`) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* panfrost: Move lcra to panfrost/utilAlyssa Rosenzweig2020-03-127-4/+3
| | | | | | | We'll want to use it for the Bifrost RA as well. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4158>
* pan/bi: Fix swizzle for second argument to ST_VARYAlyssa Rosenzweig2020-03-111-0/+1
| | | | | | | | Off-by-one. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Implement nir_op_ffmaAlyssa Rosenzweig2020-03-112-1/+2
| | | | | | | | We have native FMA which works for graphics usage (unlike Midgard where it's really reserved for compute for various reasons), let's use it. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Add dead code elimination passAlyssa Rosenzweig2020-03-114-1/+67
| | | | | | | Now that we have liveness analysis, we can cleanup the IR considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Add liveness analysis passAlyssa Rosenzweig2020-03-113-0/+99
| | | | | | | | Now that all the guts are shared with Midgard, it's just a matter of wiring it in. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Add bi_max_temp helperAlyssa Rosenzweig2020-03-111-0/+7
| | | | | | | | Instead of trying to reindex all the times, just be okay with consistent but sparse indices, then figuring out the max index is easy enough. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Add bi_next/prev_op helpersAlyssa Rosenzweig2020-03-111-0/+12
| | | | | | | From Midgard. These are surprisingly helpful. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Add bi_bytemask_of_read_components helpersAlyssa Rosenzweig2020-03-112-0/+22
| | | | | | | | Same purpose as the Midgard version, but the implementation is *dramatically* simpler thanks to our more regular IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Paste over bi_has_argAlyssa Rosenzweig2020-03-113-1/+16
| | | | | | | While we're at it, cleanup the Midgard one. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* panfrost: Sync Midgard/Bifrost control flowAlyssa Rosenzweig2020-03-1110-114/+70
| | | | | | | | We can move e v e n more code to be shared and let bi_block inherit from pan_block, which will allow us to use the shared data flow analysis. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* panfrost: Move liveness analysis to root panfrost/Alyssa Rosenzweig2020-03-115-189/+249
| | | | | | | This way we can share the code with Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Subclass midgard_block from pan_blockAlyssa Rosenzweig2020-03-119-87/+127
| | | | | | | | Promote as much as we feasibly can while keeping it Midgard/Bifrost agnostic. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Sync midgard_block field names with BifrostAlyssa Rosenzweig2020-03-114-9/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Decontextualize liveness analysis coreAlyssa Rosenzweig2020-03-111-11/+12
| | | | | | | We mostly just need the temp_count from it. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Localize `visited` trackingAlyssa Rosenzweig2020-03-112-15/+11
| | | | | | | | Instead of a property on the block, just track it within the function to minimize IR dependencies. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Implement sysvalsAlyssa Rosenzweig2020-03-112-0/+56
| | | | | | | | Now that it's all abstracted nicely with an implementation shared with Midgard, this is pretty easy to get. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/bi: Switch to panfrost_programAlyssa Rosenzweig2020-03-113-7/+4
| | | | | | | ...now that it's shared. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* panfrost: Move Midgard sysval code to common PanfrostAlyssa Rosenzweig2020-03-115-123/+160
| | | | | | | We'll use this all as-is in Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Remove dest_override sysval argumentAlyssa Rosenzweig2020-03-111-8/+5
| | | | | | | Unused, noticed while working on porting over to Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
* pan/midgard: Decontextualize midgard_nir_assign_sysval_bodyAlyssa Rosenzweig2020-03-112-16/+18
| | | | | | | Now all sysval code should be fairly generic. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4150>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 06:31:28 +0000