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* pan/midgard: Remove spill cost heuristicAlyssa Rosenzweig2019-12-121-21/+0
* pan/midgard: Simplify spillability testAlyssa Rosenzweig2019-12-121-27/+9
* pan/midgard: Split spill node selection/spillingAlyssa Rosenzweig2019-12-121-20/+30
* pan/midgard: Move spilling code out of schedulerAlyssa Rosenzweig2019-12-126-339/+379
* pan/midgard: Remove undefined behaviorTomeu Vizoso2019-12-121-1/+1
* panfrost: free spill cost table in mir_spill_registerUrja Rannikko2019-12-061-0/+2
* panfrost: add lcra_free() to free lcra stateUrja Rannikko2019-12-063-1/+25
* panfrost: free allocations in schedule_blockUrja Rannikko2019-12-061-0/+3
* panfrost: free last_read/write tables in mir_create_dependency_graphUrja Rannikko2019-12-061-0/+3
* pan/midgard: Splatter on fragment outAlyssa Rosenzweig2019-12-031-1/+20
* pan/midgard: Use lower_tex_without_implicit_lodAlyssa Rosenzweig2019-11-221-10/+3
* pan/midgard: Enable LOD lowering only on buggy chipsAlyssa Rosenzweig2019-11-221-2/+7
* pan/midgard: Describe quirk MIDGARD_BROKEN_LODAlyssa Rosenzweig2019-11-221-2/+13
* pan/midgard: Add LOD bias/clamp loweringAlyssa Rosenzweig2019-11-223-0/+101
* pan/midgard: Implement load_sampler_lod_paramaters_panAlyssa Rosenzweig2019-11-222-0/+15
* pan/midgard: Introduce quirks checksAlyssa Rosenzweig2019-11-205-10/+92
* pan/midgard: Use shader stage in mir_op_computes_derivativeAlyssa Rosenzweig2019-11-183-3/+10
* pan/midgard: Represent ld/st offset unpackedAlyssa Rosenzweig2019-11-176-47/+14
* pan/midgard: Fix masks/alignment for 64-bit loadsAlyssa Rosenzweig2019-11-174-13/+37
* pan/midgard: Expose more typesize helpersAlyssa Rosenzweig2019-11-172-1/+21
* pan/midgard: Implement non-aligned UBOsAlyssa Rosenzweig2019-11-171-5/+2
* pan/midgard: Use generic constant packing for 8/64-bitAlyssa Rosenzweig2019-11-151-1/+1
* pan/midgard: Pack 64-bit swizzlesAlyssa Rosenzweig2019-11-151-21/+63
* pan/midgard: Fix mir_round_bytemask_down for !32bAlyssa Rosenzweig2019-11-151-2/+2
* pan/midgard: Implement i2i64 and u2u64Alyssa Rosenzweig2019-11-151-1/+3
* pan/midgard: Expand 64-bit writemasksAlyssa Rosenzweig2019-11-152-7/+11
* pan/midgard: Prioritize texture registersAlyssa Rosenzweig2019-11-151-2/+13
* pan/midgard: Disassemble with old pipeline always on T720Alyssa Rosenzweig2019-11-151-2/+2
* pan/midgard: Use texture, not textureLod, on early MidgardAlyssa Rosenzweig2019-11-151-3/+4
* pan/midgard: Fix vertex texturing on early MidgardAlyssa Rosenzweig2019-11-151-0/+10
* pan/midgard: Generalize texture registers across GPUsAlyssa Rosenzweig2019-11-151-5/+2
* pan/midgard: Fix copypropagation for texturesAlyssa Rosenzweig2019-11-141-3/+4
* pan/midgard: Copypropagate vector creationAlyssa Rosenzweig2019-11-141-1/+45
* pan/lcra: Use Chaitin's spilling heuristicAlyssa Rosenzweig2019-11-141-9/+5
* pan/midgard: Compute spill costsAlyssa Rosenzweig2019-11-141-2/+13
* pan/midgard: Remove util/ra supportAlyssa Rosenzweig2019-11-135-275/+24
* pan/midgard: Integrate LCRAAlyssa Rosenzweig2019-11-133-76/+82
* pan/midgard: Implement linearly-constrained register allocationAlyssa Rosenzweig2019-11-133-0/+339
* pan/midgard: Pack load/store masksAlyssa Rosenzweig2019-11-111-2/+30
* pan/midgard: Implement nir_intrinsic_load_output_u8_as_fp16_panAlyssa Rosenzweig2019-11-111-0/+20
* pan/midgard: Identify ld_color_buffer_u8_as_fp16*Alyssa Rosenzweig2019-11-112-2/+7
* pan/midgard: Switch base for vertex texturing on T720Alyssa Rosenzweig2019-11-081-11/+16
* pan/midgard: Pass shader stage to disassemblerAlyssa Rosenzweig2019-11-083-3/+4
* pan/midgard: Disassemble half-steps correctlyAlyssa Rosenzweig2019-11-081-3/+15
* pan/midgard: Fix printing of half-registers in texture opsAlyssa Rosenzweig2019-11-081-35/+32
* panfrost: Pipe the GPU ID into compiler and disassemblerTomeu Vizoso2019-11-075-5/+8
* pan/midgard: Extend default_phys_reg to !32-bitAlyssa Rosenzweig2019-11-041-5/+5
* pan/midgard: Extend swizzle packing for vec4/16-bitAlyssa Rosenzweig2019-11-041-3/+24
* pan/midgard: Extend offset_swizzle to non-32-bitAlyssa Rosenzweig2019-11-041-3/+4
* pan/midgard: offset_swizzle doesn't need dstsizeAlyssa Rosenzweig2019-11-041-9/+9
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