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* pan/midgard: Use lower_tex_without_implicit_lodAlyssa Rosenzweig2019-11-221-10/+3
| | | | | | | | | | | Just a bit of cleanup. lower_tex can do this lowering for us, which should also eliminate some special cases (one less thing to fix if we ever need texturing in tess/geom/etc, perhaps?) Closes #2133 Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Enable LOD lowering only on buggy chipsAlyssa Rosenzweig2019-11-221-2/+7
| | | | | | | | T720 and earlier need this workaround, so check the quirk before lowering. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Describe quirk MIDGARD_BROKEN_LODAlyssa Rosenzweig2019-11-221-2/+13
| | | | | | | Corresponds to errata #10471, applies to T6xx and T720. Fixed in T760. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Add LOD bias/clamp loweringAlyssa Rosenzweig2019-11-223-0/+101
| | | | | | | | | We fetch the info with the new intrinsic and lower with ALU ops for txl instructions, which seemingly correspond to "TEXGRD" instructions (what we call textureLod). Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Implement load_sampler_lod_paramaters_panAlyssa Rosenzweig2019-11-222-0/+15
| | | | | | | | We can stuff this information in as parametrized system values, like we currently do texture size and SSBO addresses. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Introduce quirks checksAlyssa Rosenzweig2019-11-205-10/+92
| | | | | | | | | | | | | Rather than open-coding checks on gpu_id in the compiler, let's track quirks applying to whatever we're compiling for, to allow us to manage the complexity of many heterogenous GPUs in the compiler. It was discovered that a workaround used on T720 is also required on T820 (and presumably T830), so let's fix this. This will also decrease friction as we continue improving T720 support. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Use shader stage in mir_op_computes_derivativeAlyssa Rosenzweig2019-11-183-3/+10
| | | | | | | A 'normal' texture op may be emitted in a vertex shader on T720 but it still doesn't take any derivatives. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Represent ld/st offset unpackedAlyssa Rosenzweig2019-11-176-47/+14
| | | | | | | This simplifies manipulation of the offsets dramatically, fixing some UBO access related bugs. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix masks/alignment for 64-bit loadsAlyssa Rosenzweig2019-11-174-13/+37
| | | | | | | | These need to be handled with special care. Oh, Midgard, you're *extra* special. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Expose more typesize helpersAlyssa Rosenzweig2019-11-172-1/+21
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement non-aligned UBOsAlyssa Rosenzweig2019-11-171-5/+2
| | | | | | The field is more fine-grained than we had assumed. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Use generic constant packing for 8/64-bitAlyssa Rosenzweig2019-11-151-1/+1
| | | | | | | Eventually, we will want to combine constants across types, but for now let's not break the world. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pack 64-bit swizzlesAlyssa Rosenzweig2019-11-151-21/+63
| | | | | | | 64-bit ops have their own funky swizzles. Let's pack them, both for native 64-bit sources as well as extended 32-bit sources. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix mir_round_bytemask_down for !32bAlyssa Rosenzweig2019-11-151-2/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement i2i64 and u2u64Alyssa Rosenzweig2019-11-151-1/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Expand 64-bit writemasksAlyssa Rosenzweig2019-11-152-7/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Prioritize texture registersAlyssa Rosenzweig2019-11-151-2/+13
| | | | | | | | | | On newer GPUs, this is a no-op. On older GPUs, this prevents needless spilling since texture registers are shared with a subset of work registers. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Tested-by: Andre Heider <[email protected]>
* pan/midgard: Disassemble with old pipeline always on T720Alyssa Rosenzweig2019-11-151-2/+2
| | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Tested-by: Andre Heider <[email protected]>
* pan/midgard: Use texture, not textureLod, on early MidgardAlyssa Rosenzweig2019-11-151-3/+4
| | | | | | | | We have to disable the fixup. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Tested-by: Andre Heider <[email protected]>
* pan/midgard: Fix vertex texturing on early MidgardAlyssa Rosenzweig2019-11-151-0/+10
| | | | | | | | We use a different set of texture registers, probably to save hardware. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Tested-by: Andre Heider <[email protected]>
* pan/midgard: Generalize texture registers across GPUsAlyssa Rosenzweig2019-11-151-5/+2
| | | | | | | | | Early Midgard uses a different set of texture registers; let's not hardcode. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]> Tested-by: Andre Heider <[email protected]>
* pan/midgard: Fix copypropagation for texturesAlyssa Rosenzweig2019-11-141-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | total instructions in shared programs: 3562 -> 3457 (-2.95%) instructions in affected programs: 575 -> 470 (-18.26%) helped: 16 HURT: 0 helped stats (abs) min: 1 max: 14 x̄: 6.56 x̃: 10 helped stats (rel) min: 5.71% max: 24.56% x̄: 16.83% x̃: 18.87% 95% mean confidence interval for instructions value: -9.07 -4.06 95% mean confidence interval for instructions %-change: -19.00% -14.66% Instructions are helped. total bundles in shared programs: 1846 -> 1830 (-0.87%) bundles in affected programs: 338 -> 322 (-4.73%) helped: 16 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 2.50% max: 20.00% x̄: 8.85% x̃: 3.33% 95% mean confidence interval for bundles value: -1.00 -1.00 95% mean confidence interval for bundles %-change: -13.02% -4.67% Bundles are helped. total quadwords in shared programs: 3191 -> 3144 (-1.47%) quadwords in affected programs: 606 -> 559 (-7.76%) helped: 16 HURT: 0 helped stats (abs) min: 1 max: 14 x̄: 2.94 x̃: 3 helped stats (rel) min: 5.17% max: 22.22% x̄: 11.20% x̃: 5.62% 95% mean confidence interval for quadwords value: -4.58 -1.29 95% mean confidence interval for quadwords %-change: -15.16% -7.24% Quadwords are helped. total registers in shared programs: 312 -> 303 (-2.88%) registers in affected programs: 27 -> 18 (-33.33%) helped: 9 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33% 95% mean confidence interval for registers value: -1.00 -1.00 95% mean confidence interval for registers %-change: -33.33% -33.33% Registers are helped. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Copypropagate vector creationAlyssa Rosenzweig2019-11-141-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | total instructions in shared programs: 3457 -> 3431 (-0.75%) instructions in affected programs: 787 -> 761 (-3.30%) helped: 14 HURT: 0 helped stats (abs) min: 1 max: 12 x̄: 1.86 x̃: 1 helped stats (rel) min: 1.01% max: 11.11% x̄: 9.22% x̃: 11.11% 95% mean confidence interval for instructions value: -3.55 -0.16 95% mean confidence interval for instructions %-change: -11.41% -7.03% Instructions are helped. total bundles in shared programs: 1830 -> 1826 (-0.22%) bundles in affected programs: 279 -> 275 (-1.43%) helped: 2 HURT: 0 total quadwords in shared programs: 3144 -> 3121 (-0.73%) quadwords in affected programs: 645 -> 622 (-3.57%) helped: 13 HURT: 0 helped stats (abs) min: 1 max: 11 x̄: 1.77 x̃: 1 helped stats (rel) min: 2.09% max: 16.67% x̄: 12.61% x̃: 14.29% 95% mean confidence interval for quadwords value: -3.45 -0.09 95% mean confidence interval for quadwords %-change: -15.43% -9.79% Quadwords are helped. total registers in shared programs: 303 -> 301 (-0.66%) registers in affected programs: 14 -> 12 (-14.29%) helped: 2 HURT: 0 Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/lcra: Use Chaitin's spilling heuristicAlyssa Rosenzweig2019-11-141-9/+5
| | | | | | | | | | | | | | | | | Not much of a difference but slightly better and slightly less arbitrary. total instructions in shared programs: 3560 -> 3559 (-0.03%) instructions in affected programs: 44 -> 43 (-2.27%) helped: 1 HURT: 0 total bundles in shared programs: 1844 -> 1843 (-0.05%) bundles in affected programs: 23 -> 22 (-4.35%) helped: 1 HURT: 0 Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Compute spill costsAlyssa Rosenzweig2019-11-141-2/+13
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Remove util/ra supportAlyssa Rosenzweig2019-11-135-275/+24
| | | | | | It's now unused, in favour of LCRA. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Integrate LCRAAlyssa Rosenzweig2019-11-133-76/+82
| | | | | | | Pretty routine, we do have a hack to force swizzle alignment for !32-bit for until we implement !32-bit the right way. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Implement linearly-constrained register allocationAlyssa Rosenzweig2019-11-133-0/+339
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pack load/store masksAlyssa Rosenzweig2019-11-111-2/+30
| | | | | | | | | While most load/store operations on 32-bit/vec4 intriniscally, some are not and have special type-size-dependent semantics for the mask. We need to convert into this native format. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Implement nir_intrinsic_load_output_u8_as_fp16_panAlyssa Rosenzweig2019-11-111-0/+20
| | | | | | | | We can use the native Midgard ops for this, depending what chip we're on. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Identify ld_color_buffer_u8_as_fp16*Alyssa Rosenzweig2019-11-112-2/+7
| | | | | | | | | | There are two versions of this opcode, depending what version of the ISA you're using. I'm not sure if there's a semantic difference; I think there might be some slight subtleties but it's too early to know at this stage. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Switch base for vertex texturing on T720Alyssa Rosenzweig2019-11-081-11/+16
| | | | | | | | There aren't texture pipeline registers anymore; instead, space is shared with work and ldst registers for output and input respectively. We need to shift the base registers to represent this correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Pass shader stage to disassemblerAlyssa Rosenzweig2019-11-083-3/+4
| | | | | | | Vertex texturing behaves differently from fragment texturing on some GPUs. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Disassemble half-steps correctlyAlyssa Rosenzweig2019-11-081-3/+15
| | | | | | | The meaning of some bits shifts; we need to account for this to print swizzles sanely. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix printing of half-registers in texture opsAlyssa Rosenzweig2019-11-081-35/+32
| | | | | | | We were using old style half-registers; let's update that to be consistent, preparing us for more disassmbler changes in this area. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Pipe the GPU ID into compiler and disassemblerTomeu Vizoso2019-11-075-5/+8
| | | | Signed-off-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Extend default_phys_reg to !32-bitAlyssa Rosenzweig2019-11-041-5/+5
| | | | | | We can pass through a size. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend swizzle packing for vec4/16-bitAlyssa Rosenzweig2019-11-041-3/+24
| | | | | | | | We would like to pack not just xyzw swizzles but also efgh swizzles. This should work for vec4/16-bit. More work will be needed to pack swizzles for vec8/16-bit and even more work for 8-bit, of course. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Extend offset_swizzle to non-32-bitAlyssa Rosenzweig2019-11-041-3/+4
| | | | | | We take a size parameter; use it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: offset_swizzle doesn't need dstsizeAlyssa Rosenzweig2019-11-041-9/+9
| | | | | | This argument should be omitted. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add bizarre corner caseAlyssa Rosenzweig2019-11-041-1/+8
| | | | | | Someone really needs to look into this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Compute bundle interferenceAlyssa Rosenzweig2019-11-041-0/+57
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix quadword_count handlingAlyssa Rosenzweig2019-11-043-4/+8
| | | | | | Spilling can mess with this considerably. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Validate tags when branchingAlyssa Rosenzweig2019-11-041-6/+32
| | | | | | | | | | | | | | | | | | Midgard prefetches instructions based on tag (ALU, LD/ST, texture * size). To do so, the shader descriptor specifies the tag of the first instruction, all instructions specify the tag of the next linear instruction is, and all branches explicitly specify the tag of the branch target. If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously refers to this problem, but it's still annoying to try to work out all the branch targets in your head to debug. Instead, let's track the tags of various blocks over time, so we can automatically validate tags of branch targets, to make INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Eliminate blank_alu_srcAlyssa Rosenzweig2019-11-016-36/+22
| | | | | | We don't need it in practice, so this is some more cleanup. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Refactor swizzlesAlyssa Rosenzweig2019-11-0113-385/+258
| | | | | | | | Rather than having hw-specific swizzles encoded directly in the instructions, have a unified swizzle arary so we can manipulate swizzles generically. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add a dummy source for loadsAlyssa Rosenzweig2019-11-013-29/+11
| | | | | | | | | | | | | | We want symmetry between loads and stores, so we add a dummy source. So we get, e.g. st_int4 _, val, arg_1, arg_2 ld_int4 dest, _, arg_1, arg_2 Semantically, this dummy source represents the data itself, as if the load is simply a move. That means it has a swizzle that acts as a source. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Remove OP_IS_STORE_VARYAlyssa Rosenzweig2019-11-011-7/+0
| | | | | | Unused. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Express allocated registers as offsetsAlyssa Rosenzweig2019-10-251-104/+62
| | | | | | | | | | Rather than supplying a mask/swizzle to compose with the original, just supply the offset of the allocated register so we can directly offset the mask/swizzle, without resorting to composition. This is simpler, cleaner, and will generalize to non-32-bit. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Expose more typesize manipulation routinesAlyssa Rosenzweig2019-10-252-2/+4
| | | | | | These internal mir.c routines will help the RA. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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