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While most load/store operations on 32-bit/vec4 intriniscally, some are
not and have special type-size-dependent semantics for the mask. We need
to convert into this native format.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Tomeu Vizoso <[email protected]>
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We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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Rather than having hw-specific swizzles encoded directly in the
instructions, have a unified swizzle arary so we can manipulate swizzles
generically.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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Miscellaneous minor issues flagged by cppcheck.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Tomeu Vizoso <[email protected]>
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This is just a bit of refactoring to simplify MIR.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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We need to keep the helper invocations alive.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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Implement the fdd* and fdd* opcodes in the Midgard compiler.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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The swizzle should be taken on the masked component, rather than
unconditionally X.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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In preparation for a Panfrost-based non-Gallium driver (maybe
Vulkan...?), hoist everything except for the Gallium driver into a
shared src/panfrost. Practically, that means the compilers, the headers,
and pandecode.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
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