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* panfrost/midgard: Use a union to manipulate embedded constantsBoris Brezillon2020-01-221-0/+19
| | | | | | | | | | | | Each instruction bundle can contain up to 16 constant bytes. The meaning of those byte is instruction dependent: it depends on the instruction native type (int, uint or float) and the instruction reg_mode (8, 16, 32 or 64 bit). Those different layouts can be exposed as a union to facilitate constants manipulation. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3478>
* panfrost: Identify un/pack colour opcodesAlyssa Rosenzweig2020-01-181-0/+6
| | | | | | | | | We still need to identify formats in the disassembler, but this will at least get the opcode name clear. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3462> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3462>
* pan/midgard: Identity ld_color_buffer as 32-bitAlyssa Rosenzweig2020-01-021-1/+1
| | | | | | I'm not sure why I mistakenly identified it as an 8-bit op before. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Do witchcraft on texture offsetsAlyssa Rosenzweig2019-12-241-6/+20
| | | | | | | | | | | My latest divination spell has uncovered a pattern in the aether. Although the swizzle is unaligned, its format is otherwise standard. Document this, removing the old incorrect understanding of the swizzle (which coincided on common special swizzles only). Fixes dEQP-GLES3.functional.shaders.texture_functions.texelfetchoffset.sampler2d_fixed_fragment Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Identify ld_color_buffer_u8_as_fp16*Alyssa Rosenzweig2019-11-111-1/+5
| | | | | | | | | | There are two versions of this opcode, depending what version of the ISA you're using. I'm not sure if there's a semantic difference; I think there might be some slight subtleties but it's too early to know at this stage. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* pan/midgard: Identify 64-bit atomic opcodesAlyssa Rosenzweig2019-10-201-0/+10
| | | | | | They are symmetric to their 32-bit counterparts, just shifted. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Identify and disassemble indirect texture/samplerAlyssa Rosenzweig2019-08-211-1/+11
| | | | | | | | | | | | | A pair of special flags can turn the texture/sampler handle fields into register selects. This means code like: texture(uTextures[hr28.w], ...) can be compiled to something like: texture ..., fsampler[hr28.w], texture[hr28.w] Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Treat cubemaps "stores" as loadsAlyssa Rosenzweig2019-08-191-5/+4
| | | | | | | It's always been ambiguous which they are, but their primary register is their output, not their input; therefore, they are loads. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Identify UBO/SSBO op symmetryAlyssa Rosenzweig2019-08-141-3/+13
| | | | | | It's the same thing, just shifted. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Rename ld_global_id -> ld_compute_idAlyssa Rosenzweig2019-08-121-2/+2
| | | | | | It's used for more general loads within a compute shader. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Disassemble load/store barrel shiftAlyssa Rosenzweig2019-08-081-1/+8
| | | | | | Arm assembly intensifies. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Print texture outmodAlyssa Rosenzweig2019-08-021-1/+4
| | | | | | I have no idea who thought this was a good idea. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Decode register/component in load/store argumentAlyssa Rosenzweig2019-08-021-1/+16
| | | | | | 3-bits out of 8 down! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Split ld/st unknown to arg_1/arg_2 fieldsAlyssa Rosenzweig2019-08-021-1/+8
| | | | | | | | | The 16-bit field can be decomposed to two independent 8-bit fields, each representing a single (additional) argument to the load/store op, generally used for encoding registers. Addressable registers here are substantially limited compared to the main register in a load/store op. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Flip texture/sampler fieldsAlyssa Rosenzweig2019-07-311-1/+1
| | | | | | | | We had them backwards in both the command stream and the Midgard stack. In OpenGL ES 2.0, they're always the same, but in Vulkan/later-GL/CL they diverge so we can fix this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add units for more instructionsAlyssa Rosenzweig2019-07-311-1/+1
| | | | | | | For everything but freduce, we have some sense of what units the instruction takes. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix ball/bany opcode tableAlyssa Rosenzweig2019-07-311-3/+3
| | | | | | | This were seriously messed up beyond all recognition. How we're passing shaders.random.* is a mystery. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Document branch combination LUTAlyssa Rosenzweig2019-07-311-0/+13
| | | | | | This took way longer to figure out than it should have.. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add support for disassembling derivativesAlyssa Rosenzweig2019-07-301-0/+10
| | | | | | They're just texture ops. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix flipped register bias fieldsAlyssa Rosenzweig2019-07-261-13/+4
| | | | | | | | We mixed up component_lo and full, which made it appear that we had less freedom in RA than we actually do. Fix this to fix some disassemblies as well as prepare for RA with the bias field. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Use generic outmod typeAlyssa Rosenzweig2019-07-121-1/+1
| | | | | | | It could be midgard_outmod_float or midgard_outmod_int; don't assume it's one or the other. Fixes -Wenum-conversion warnings. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move non-Gallium files outside of GalliumAlyssa Rosenzweig2019-07-101-0/+646
In preparation for a Panfrost-based non-Gallium driver (maybe Vulkan...?), hoist everything except for the Gallium driver into a shared src/panfrost. Practically, that means the compilers, the headers, and pandecode. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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