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* panfrost: Dynamically allocate array of texture pointersTomeu Vizoso2020-01-021-2/+0
| | | | | | | | With 3D textures we can have lots of layers, so better allocate it dynamically at runtime. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Identify glProvokingVertex flagAlyssa Rosenzweig2019-12-301-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove 32-bit next_job pathAlyssa Rosenzweig2019-12-271-5/+1
| | | | | | | | | | It has been unused for a while; let's just remove the abstraction. Technically the hardware does support 32-bit job descriptors, but we don't and we can't keep them from breaking so let's not pretend they work. Signed-off-by: Alyssa Rosenzweig <[email protected]> Suggested-by: Boris Brezillon <[email protected]>
* panfrost; Update comment about work/uniform_countAlyssa Rosenzweig2019-12-271-3/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove mali_alt_funcAlyssa Rosenzweig2019-12-271-15/+3
| | | | | | | | | | There's only one way to encode comparison functions in the command stream, not two. It's just that the semantics for texture comparisons are flipped from the semantics of stencil comparison. We can factor out that flip to common Panfrost code, rather than tying it to a second Gallium routine. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement remaining texture wrap modesAlyssa Rosenzweig2019-12-271-5/+9
| | | | | | | | Somehow we have native hardware for all of these. Suspected by staring at the bit pattern; confirmed by poking in various texture wrap modes into the textures mesa demo and seeing what happens. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Inline away MALI_NEGATIVEAlyssa Rosenzweig2019-12-271-4/+0
| | | | | | It's an awfully fancy way to add one... Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove MALI_ATTR_INTERNALAlyssa Rosenzweig2019-12-271-1/+0
| | | | | | | It's a relic from before we understood the varying builtins. It should never actually come up if the builtins are decoded correctly. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Update information on fixed attributes/varyingsAlyssa Rosenzweig2019-12-271-3/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove MALI_SPECIAL_ATTRIBUTE_BASE definesAlyssa Rosenzweig2019-12-271-5/+0
| | | | | | | | | These are conventions by the blob (a convention we happent to follow). They are not at all intrinsic to the hardware, so now that the convention is implemented within the Midgard stack, these defines are wholly unused. Remove them. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Handle gl_VertexID/gl_InstanceIDAlyssa Rosenzweig2019-12-241-3/+4
| | | | | | | | | Just like varyings have special records for point coordinates (etc), attributes have special records for vertex/instance ID. We can parse these fairly easily, although they don't line up exactly with normal attribute records. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Pack invocation_shifts manually instead of a bit fieldAlyssa Rosenzweig2019-12-161-7/+10
| | | | | | | | gcc generates exceptionally bad code for panfrost_pack_work_groups_fused otherwise ... although that routine is somehow still hot ... Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>
* panfrost: Remove fbd_type enumAlyssa Rosenzweig2019-12-161-6/+3
| | | | | | | | Just use the MALI_MFBD tag directly; it's clean. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
* panfrost: Split stack_shift nibble from unk0Alyssa Rosenzweig2019-12-121-1/+2
| | | | | | | It's conceptually independent from the upper part (which is not yet understood, but for spilling generally remains equal to 0x1e). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rename unknown_address_0 -> scratchpadAlyssa Rosenzweig2019-12-121-1/+2
| | | | | | It's the analogue pointer in SFBD. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rename SET_VALUE to WRITE_VALUEAlyssa Rosenzweig2019-12-061-4/+4
| | | | | | | | | See https://lists.freedesktop.org/archives/dri-devel/2019-December/247601.html Write value emphasises that it's just a generic write primitive. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Update SET_VALUE with information from igtAlyssa Rosenzweig2019-12-061-2/+9
| | | | | | | It's not a tiler specific initialization; it's a generic GPU-side write primitive that may be used for tiler reset on midgard. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove blend shader hackAlyssa Rosenzweig2019-12-031-2/+1
| | | | | | This is no longer used. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement pan_tiler for non-hierarchy GPUsAlyssa Rosenzweig2019-12-031-1/+9
| | | | | | | | | | | | | | | | The algorithm is as described. Nothing fancy here, just need to add some new code paths depending on which model we're running on. Tomeu: - Also disable tiling when !hierarchy and !vertex_count - Avoid creating polygon lists smaller than the minimum when vertex_count > 0 but tile size smaller than 16 byte - Take into account tile size when calculating polygon list size for !hierarchy - Allow 0-sized tiles in a single dimension Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost: Add quirks system to cmdstreamTomeu Vizoso2019-12-031-0/+67
| | | | | | | | Similarly to how it's already done in the compiler, add a way to express differences between GPU models that need to be taken into account when assembling the cmdstream. Signed-off-by: Tomeu Vizoso <[email protected]>
* panfrost: Add the lod_bias fieldAlyssa Rosenzweig2019-11-211-1/+2
| | | | | | | Enough trial and error ... just think even *more* Midgard about where this field might be! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add blend shader selection bits for MRTAlyssa Rosenzweig2019-11-131-0/+8
| | | | | | | | | | | | | This is less complicated than previously thought. Note we have no way of specifying the work register count for blend shaders; it must be strictly less than the work register count of the corresponding fragment shader (which is fine since we force the fragment shader to report a count of 16 with a blend shader as a major hack until we get register pressure down for blend shaders). TODO: pandecode the flags. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Rework format encoding on SFBDTomeu Vizoso2019-11-061-26/+38
| | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add checksum fields to SFBD descriptorTomeu Vizoso2019-11-061-1/+4
| | | | | | | During tests on T720, these fields were discovered. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASKBoris Brezillon2019-11-041-1/+1
| | | | | | | | | MALI_DEPTH_TEST should only be set when depth->writemask is true, not when the depth test is enabled. Let's rename the flag and patch panfrost_bind_depth_stencil_state() to do the right thing. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Remove unused definitions in mali-job.hAlyssa Rosenzweig2019-10-291-9/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Cleanup _shader_upper -> shaderAlyssa Rosenzweig2019-10-291-2/+1
| | | | | | I don't believe this is actually a tagged pointer; warn if it is. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement gl_FragCoord correctlyAlyssa Rosenzweig2019-08-221-6/+13
| | | | | | | | Rather than passing through the transformed gl_Position, we can use the hardware-level varying for this, which will correctly handle gl_FragCoord.w Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Validate, but do not print, index bufferAlyssa Rosenzweig2019-08-221-0/+3
| | | | | | | We don't actually care about the *contents* of the index buffer, but we would rather like to ensure it is present and of the correct size. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Validate MFBD tagsAlyssa Rosenzweig2019-08-221-5/+3
| | | | | | | | | These tags need to match up with what's actually described by the MFBD, so check this. Once this is checked, since the type and contents of the FBD are obvious from printing above, there's no need to explicitly mark off the framebuffer line. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Break up usage2 fieldAlyssa Rosenzweig2019-08-211-4/+22
| | | | | | This is another bit field describing layout. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: nr_mipmap_levels -> levelsAlyssa Rosenzweig2019-08-211-1/+1
| | | | | | No need to be so verbose. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Validate AFBC fields are zero when AFBC is disabledAlyssa Rosenzweig2019-08-211-21/+15
| | | | | | | | | There is no "chunknown" structure; that part of the union is an artefact from falsely believing vertex/tiler MFBDs could have render targets attached (they can't). These are just plain old AFBC fields, and if there is no AFBC, it's error to set these field. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Check for a number of potential issuesAlyssa Rosenzweig2019-08-211-1/+9
| | | | | | | | Verify sizes / masks / etc against something logical to cull down the trace space and automatically guard against a number of potential hazards. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Decode invalid access type upon faultAlyssa Rosenzweig2019-08-141-0/+15
| | | | | | | We don't have a good way to confirm this, but it parallels the kernel definitons for MMU faults nicely. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Note "MFBD preload disable" bitAlyssa Rosenzweig2019-08-141-1/+10
| | | | | | It's a chicken bit, as far as I can tell. Buck buck. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Take into account a index_bias for glDrawElementsBaseVertex callsRohan Garg2019-08-061-3/+18
| | | | | | | | | | | | | | Midgard does not accept a index_bias directly and relies instead on a bias correction offset (offset_bias_correction) in order to calculate the unbiased vertex index. We need to make sure we adjust offset_start and vertex_count in order to take into account the index_bias as required by a glDrawElementsBaseVertex call and then supply a additional offset_bias_correction to the hardware. Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add support for decoding gl_FrontFacingAlyssa Rosenzweig2019-08-011-1/+10
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add MALI_SAMP_NORM_COORDS flagAlyssa Rosenzweig2019-07-311-0/+5
| | | | | | | Corresponds to the normalized coordinates? flag on images in OpenCL and evidently also shows up in GL, so let's wire it in. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Simplify filter_mode definitionAlyssa Rosenzweig2019-07-311-12/+6
| | | | | | | It's just a bit field containing some flags; there's no need for all the macro magic. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Shrink "compute FBD"Alyssa Rosenzweig2019-07-311-1/+1
| | | | | | | We still don't know what it is, but from a newer trace we now know it's half the size we thought it was. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Flip texture/sampler fieldsAlyssa Rosenzweig2019-07-311-1/+1
| | | | | | | | We had them backwards in both the command stream and the Midgard stack. In OpenGL ES 2.0, they're always the same, but in Vulkan/later-GL/CL they diverge so we can fix this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add MALI_ATTR_IMAGE valueAlyssa Rosenzweig2019-07-311-0/+6
| | | | | | | Images are implemented (in part) as special attributes, so include support for decoding this. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use correct NO_DITHER field on MFBDAlyssa Rosenzweig2019-07-181-0/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use 64-bit descriptors globallyTomeu Vizoso2019-07-161-26/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Midgard supports two modes of operation, 32-bit mode and 64-bit mode. The GPU is natively 64-bit, but job descriptors can be submitted in 32-bit mode. Among other changes, 32-bit mode shortens pointer sizes to use 32-bit pointers rather than the full 64-bit range. The blob decides which mode to use based on the CPU bitness, so an armhf system uses 32-bit descriptors and an aarch64 system uses 64-bit descriptors. For a while, we mimicked this, bu inevitably this caused the 32-bit support to lag behind as our reference platform is 64-bit. To combat the code staleness, we traced an older GPU paired with a 64-bit CPU (the Midgard T720 on-board the sunxi H64). From there, we could tell which fields were really about hardware and which fields were simply reflections of the descriptor bitness. From there, we decided to remove support for 32-bit descriptors entirely, using 64-bit descriptors unconditionally. There is minimal performance penalty for this in practice, and it allows us to unify these disparate code paths. This fixes: - T860 + armhf - T820 + armhf - T760 + aarch64 And will help bringup of 1st/2nd generation Midgard regardless of CPU. [Work done by Tomeu. Commit message written by Alyssa.] v2: Add comments preserving information about the old behaviour for future reference. Fix a compiler warning. (Alyssa) Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/decode: Depth units/factor are identical to GLAlyssa Rosenzweig2019-07-111-5/+1
| | | | | | | I'm not sure why I thoughtt here was an off-by-one, other than maybe bad data collection. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move non-Gallium files outside of GalliumAlyssa Rosenzweig2019-07-102-0/+1649
In preparation for a Panfrost-based non-Gallium driver (maybe Vulkan...?), hoist everything except for the Gallium driver into a shared src/panfrost. Practically, that means the compilers, the headers, and pandecode. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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